84 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 56, NO. 1, JANUARY 2009 Power Supply Noise in Analog Audio Class D Amplifiers Wei Shu and Joseph S. Chang Abstract—A potential drawback of class D amplifiers (CDAs) is their relatively poor tolerance to power supply noise. It has been re- cently established by means of a linear model that the manifested nonlinearities due to the supply noise are the fundamental noise frequency component and second-order intermodulation compo- nents, qualified by the power supply rejection ratio (PSRR) and in- termodulation distortion (IMD), respectively. In this paper, multi- dimensional Fourier series analysis is applied to open-loop, single-, and double-feedback pulsewidth modulation CDAs, and expres- sions for PSRR, IMD, and fold-back distortion (FBD) are derived. This analysis takes into account the nonlinear pulse modulation process (unaccounted for in the linear model), and all components of PSRR and IMD nonlinearities are hence modeled. It is shown that the first-harmonic PSRR and third-order IMD components, which are usually ignored in CDAs and linear amplifiers, are signif- icant and that, under certain conditions, the third-order IMD com- ponents can be higher than the second-order IMD components. It is also shown that the loop gain should be high for high PSRR and low IMD. Furthermore, significant FBD can arise due to the in- termodulation between the supply noise, the input signal, and the carrier, and interestingly, the FBD in closed-loop CDAs is more se- rious than that in open-loop CDAs. The analyses herein are veri- fied by computer simulations and on the basis of measurements on a prototype CDA IC and on other hardware realizations. Index Terms—Class D amplifiers (CDAs), intermodulation dis- tortion (IMD) pub. I. INTRODUCTION A UDIO POWER amplifiers are increasingly based on a class D amplifier (CDA) architecture due to its substan- tially higher power-efficiency attribute over their classical linear analog class A and AB counterparts [1]. This attribute is largely due to their output-stage switching-mode operation and is par- ticularly attractive for remotely powered devices and for their small form factor. The pulse modulation techniques often em- ployed in analog CDAs include the following: 1) pulsewidth modulation (PWM) [2]; 2) pulse density modulation [3]; and 3) bang-bang modulation [4]; digital CDAs are often based on 1) and 2) [5], [6]. Among these approaches, the PWM approach is arguably the most prevalent due to its relatively lower switching frequency, high stability at near-100% modulation [7], and its simpler architecture, and is the approach of interest in this paper. Power supply noise, often qualified by power supply rejec- tion ratio (PSRR), and its mechanisms are well established for Manuscript received June 1, 2006; revised November 30, 2007. First pub- lished April 18, 2008; current version published February 4, 2009. This paper was recommended by Associate Editor P. Carbone. The authors are with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798, Singapore (e-mail: shuw0001@ntu.edu.sg; ejschang@ntu.edu.sg). Digital Object Identifier 10.1109/TCSI.2008.921055 linear amplifiers [8]. The supply noise has been recently recog- nized [9] as a drawback of CDAs compared with their linear counterparts and may otherwise require expensive hardware solutions such as highly stabilized low-noise power supplies. This drawback arises primarily because of the architecture of the switching-mode output stage. For example, the fundamental PSRR of an open-loop CDA is merely 6 dB [10], [11]; in this paper, the fundamental PSRR refers to the PSRR due to the nonlinear component whose frequency is the same frequency as the frequency of supply noise, typically 100 Hz or 120 Hz. On the basis of a linear model [11] in the Laplace domain, we have recently modeled the mechanisms and derived ana- lytical expressions for the fundamental PSRR of the following three prevalent CDA design topologies: 1) open-loop CDA; 2) single-feedback (1FB-) CDA; and 3) double-feedback (2FB-) CDA. Topologies 2) and 3) are closed-loop CDAs. In addition to the supply noise at the CDA output qualified by PSRR, we have recently shown [11] that the supply noise may further intermodulate with the input signal at the output stage and manifest into intermodulation distortion (IMD). In this case, the IMD is the second-order IMD wherein the frequen- cies of the nonlinear components are equal to the input signal frequency plus/minus the supply noise frequency; note the in- termodulation signals herein and the definition of IMD as op- posed to the usual IMD due to the intermodulation between two input signals. The manifested IMD, although not well recog- nized within the electronics community, can be serious. For ex- ample, the second-order IMD of an open-loop CDA is 9 dB for the worst-case condition where the modulation index and with respect to the supply noise. Although the earlier derived linear model [11] for PSRR and IMD is intuitive and useful, as it provides insight into the mech- anisms and the pertinent parameters therein, the linear model is incomplete in the sense that it does not model all nonlin- earities due to the supply noise, including the harmonic PSRR components and the higher order IMD components. This short- coming is primarily because the PWM operation/process was assumed to be linear when it is actually nonlinear (as modeled by Fourier series). In this paper, the harmonic PSRR refers to the PSRR whose components are at multiple integers of the supply noise frequency, and the higher order IMD refers to the IMD whose components are at frequencies that are the input signal frequency plus/minus the multiple integers of the supply noise frequency. The additional nonlinear components, namely, the harmonic PSRR and higher order IMD, can be significant in densely populated system-on-chip environments where the supply noise may include high-frequency components (as op- posed to only the fundamental low-frequency noise) due to the 1549-8328/$25.00 © 2009 IEEE