Compact Iterative Field Effect Transistor Model M. S. Shur * , V.O. Turin * , D. Veksler ** , T. Ytterdal *** , B. Iñiguez **** , and W. Jackson ***** * Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, New York 12180-3590, USA, shurm@rpi.edu ** Department of Physics, Rensselaer Polytechnic Institute, Troy, New York 12180-3590, USA, veksld@rpi.edu *** Department of Physical Electronics, Norwegian University of Science and Technology, N-7034 Trondheim, Norway, ytterdal@iet.ntnu.no **** EEEA, Universitat Rovira i Virgili, 43007 Tarragona, Spain, benjamin.iniguez@urv.ne ***** Hewlett-Packard Laboratories, Palo Alto, California 94304, USA, warren.jackson@hp.com ABSTRACT We propose an iterative approach that uses a simple seven-parameter model (based on Unified Charge Control Model – UCCM [1]). This first-order approximation model accounts for the velocity saturation in the device channel, for source and drain series resistance, and for drain barrier lowering. The Universal Current Model (UCM) is used for the output current-voltage characteristics. All other non ideal effects are accounted for using iterations based on the values of the TFT current obtained using this basic model. As examples, we consider the effects of the source and drain series resistance on the linearity of the current voltage characteristics at low drain biases, the effect of the current dependent source series resistance, and the effect of the gate-dependent field effect mobility on the current-voltage characteristics. Keywords: thin film transistors, compact model, gate dependent field effect mobility 1 BASIC MODEL Compact models for field effect transistors should satisfy two conflicting requirements. On one hand, they should be simple enough and should contain a small number of physics-based parameters to be suitable for parameter extraction. On the other hand, they should accurately account for complicated device phenomena and accurately reproduce device characteristics over many orders of magnitude of the device current and for a wide range of frequencies. This latter requirement is especially important for modeling analog or mixed analog/digital circuits. We propose an iterative approach that uses a simple six- parameter model (based on Unified Charge Control Model – UCCM [1]). This first-order approximation model accounts for the velocity saturation in the device channel, for source and drain series resistance, and for drain barrier lowering. The Universal Current Model (UCM) is used for the output current-voltage characteristics. This model is suitable for parameter extraction and allows for excellent conversion even at very small feature sizes because of the continuity of all derivatives of the current and voltage with respect to extrinsic gate and drain voltages. The model can be augmented by the unified Meyers capacitance model that accounts for capacitance dispersion at high frequencies via Elmore constants. Using this model, we derive the intrinsic drain and gate bias and corresponding drain current and gate-to-source and gate-to-drain capacitance. These values are used for the second iteration model to account for such effects as the channel mobility dependence on the intrinsic gate and drain bias. We start from our MOS saturation model using the following equation from [1]: ( ) 2 2 1 1 2 / gt sat s gt s gt gt L V I RV RV V V β β β = + + + + (1) At small V ds (in the linear regime) ch ds I gV = (2) Here = 1 chi ch sd chi s mi g g R g Rg + + (3) R sd = R s + R d and = = chi GT mi DS g V g V β β (4) Therefore, g mi is much smaller than g chi at small V ds << V gt and 1 gt ch sd gt V g R V β β ≈ + (5) (provided that gt ds s gt VVR V β << ). Now we can use the following general expression for the current [1] 648 NSTI-Nanotech 2006, www.nsti.org, ISBN 0-9767985-8-1 Vol. 3, 2006