1822 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002 A 5-Gb/s 0.25- m CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Member, IEEE, Bong-Joon Lee, Deog-Kyoon Jeong, Member, IEEE, Wonchan Kim, Young-June Park, Member, IEEE, and Gijung Ahn, Member, IEEE Abstract—This paper describes a clock/data recovery circuit (CDR) incorporating a variable-interval 3 -oversampling method for enhanced high-frequency jitter tolerance. The CDR traces the eye-opening region to place the data-sampling clock exactly at the center of data eye, responding to the shape and magnitude of jitter. A sampler with a pair of input-holding switches enables high-speed data sampling with reduced dynamic offset voltage. From the lin- earized model of the phase detector, the loop dynamics of the CDR is analyzed. Integrated in a single-chip transceiver with 0.25- m CMOS technology, the CDR operates at a data rate of 5 Gb/s. The CDR shows a bit error rate of less than 10 when the magnitude of data jitter reaches 60.5% of a bit time. Index Terms—Clock/data recovery, data eye, deterministic jitter, high-frequency jitter tolerance, phase detector, sampler, serial link, variable-interval oversampling. I. INTRODUCTION T HERE has been rapid expansion of serial link systems such as Gigabit Ethernet, Fiber Channel, SONET, IEEE1394, backplane interconnect, and so on. In those applications, the clock/data recovery circuit (CDR) extracts the clock and regen- erates data from the input data stream, where its phase detector (PD) locates the sampling clock appropriately so that bit error rate (BER) can be minimized. In a CDR for lower data rate, where device bandwidth does not limit the operating speed, a digital phase-locked loop (PLL) can be used for excellent jitter suppression or jitter tolerance [1], [2]. The PLL uses a local clock whose frequency is several times higher than the data rate [1] or multiphase clocks with a frequency equal to the data rate [2]. With the increase of data rate, however, delay cells cannot meet the speed requirements of those schemes. A 3 -oversam- pling method was utilized to cope with high data rates [3], [4], Manuscript received March 29, 2002; revised June 20, 2002. S.-H. Lee, S. Kim, and Y. Moon, were with the School of Electrical Engineering and Computer Science, Seoul National University, Shinlim-Dong, Gwanak-Gu, Seoul 151-742, Korea. They are now with Silicon Image, Inc., Sunnyvale, CA 94085 USA (e-mail: shlee@siimage.com; sjkim@siimage.com; ysmoon@siimage.com). M.-S. Hwang, Y. Choi, B.-J. Lee, D.-K. Jeong, W. Kim, and Y.-J. Park are with the School of Electrical Engineering and Computer Science, Seoul Na- tional University, Shinlim-Dong, Gwanak-Gu, Seoul 151-742, Korea (e-mail; msh@griffin.snu.ac.kr; arbutus@iclab.snu.ac.kr; bjlee@griffin.snu.ac.kr; dkjeong@ee.snu.ac.kr; wkim@iclab.snu.ac.kr; yjpark@ee.snu.ac.kr). G. Ahn is with Silicon Image, Inc., Sunnyvale, CA 94085 USA (e-mail: mrahn@siimage.com). Digital Object Identifier 10.1109/JSSC.2002.804342 but it exhibits deteriorated phase quantization error due to the increased phase interval. The tracking-type CDRs have been in wide use for gigabit data rates [5]–[8] because they do not suffer from phase quan- tization error. These CDRs can be categorized into two groups according to the phase detection method: one is the linear CDR [5], [6] and the other is the binary CDR [7], [8]. The linear CDR adopts a linear PD to align falling edges of the sampling clock to data transition edges, while rising edges are used to trigger the sampler. In spite of the well-known loop design method- ology [9] similar to that of a charge pump PLL [10], there are some difficulties in the physical implementation of the CDR with CMOS technology. It needs a limiting preamplifier at the input stage, resulting in increased jitter due to limited device bandwidth. Also, there is a timing offset between the data and sampling clock caused by the setup/hold-timing uncertainty of the sampler. The timing offset should be compensated for in the design stage with the aid of simulation and empirical estimation, still susceptible to process-voltage-and-temperature (PVT) vari- ation. On the contrary, the binary CDR inherently compensates for the timing offset since it uses sampled data for phase detec- tion. Also, its phase detector does not require a limiting pream- plifier. Furthermore, the binary CDR can utilize a multibit sam- pling in one clock cycle, making it possible to operate at higher data rates with low-frequency clocks. The work of this paper is motivated from two issues related to a conventional binary CDR. Though the binary CDR has advan- tages for high-speed implementation with CMOS technology, it still cannot maintain optimum BER performance under se- vere and asymmetric jitter environment. This paper introduces a new CDR to overcome the jitter tolerance problem of the bi- nary CDR. The CDR is primarily similar to the binary CDR and inherits the advantages of the binary CDR. However, it adopts a new phase detection method to sample data at the center of data eye irrespective of the magnitude and shape of jitter. As another issue, a conventional linear PLL theory is not useful for the analysis of the binary CDR because of its binary quantized phase detection. Therefore, the design of the loop parameters has been dependent upon iterative simulations of the loop be- havior, which is cumbersome and time-consuming. This paper presents a linear model of the CDR based on the analysis of the time-averaged behavior of the phase detector. Section II introduces the jitter tolerance issue of a conven- tional binary CDR. In Section III, the architecture and phase 0018-9200/02$17.00 © 2002 IEEE