This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 14-nm FinFET Technology for Analog and RF Applications Jagar Singh , J. Ciavatti, K. Sundaram, J. S. Wong, A. Bandyopadhyay, X. Zhang, S. Li, A. Bellaouar, J. Watts , J. G. Lee, and S. B. Samavedam Abstract — This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a F t /F max of 314/180 GHz and 285/140 GHz for N and PFinFET device, respectively. The double-side gate contact structure with contact on either end of active gate enhances the peak F max performance to 227 and 195 GHz for both N and PFinFET devices, respectively. A significant boost in the PFinFET RF performance is observed compared to 28-nm planar PFET, which is attributed to the source/drain SiGe epitaxy stressor that results in higher hole carrier mobility. On the other hand, the thin channel body of FinFET structure facilitates a better electrostatic control of gate over the channel region and hence suppresses short channel effects including the drain-induced barrier lowering. Consequently, a significantly higher self-gain (G m /G ds ) 40 and 34 for both NFinFET and PFinFET is achieved. In addition, N/PFinFETs demonstrate superior 1/f noise of 17/35 fV 2 μm 2 /Hz at 1 kHz compared to 171/106 fV 2 μm 2 /Hz of 28-nm planar N/PFETs. To extend the low-voltage operation and power saving of FinFET RF platform, ultralow V t N/PFinFETs in the range of 50 mV V t s are also developed. Furthermore, a deep n-well process is added to the platform to provide device and circuit isolation from substrate and supply noise, while realizing the creation of new devices such as vertical NPN, PCAP, and high breakdown voltage deep n-well junction diodes. Overall, a superior F t /F max , high self-gain, low 1/f noise, and robust substrate isolation characteristics extend the capability of this new 14-nm FinFET technology to the analog and RF circuit applications. Index Terms— 5G mobile communication, 14-nm and 28-nm technology, deep n-well isolation, FinFET, logic devices, RF CMOS, wireless communication. Manuscript received July 18, 2017; revised September 5, 2017, October 5, 2017, and November 8, 2017; accepted November 20, 2017. This work was supported by Fab8 Technology Development, GlobalFoundries, Malta, NY 12020 USA. The review of this paper was arranged by Editor P. J. Fay. (Corresponding author: Jagar Singh.) J. Singh, J. Ciavatti, X. Zhang, J. Watts, J. G. Lee, and S. B. Samavedam are with GlobalFoundries, Malta, NY 12020 USA (e-mail: jagar.singh@globalfoundries.com). K. Sundaram and J. S. Wong are with GlobalFoundries, Singapore 738406. A. Bandyopadhyay is with GlobalFoundries Hopewell Junction, NY 12533 USA. S. Li is with GlobalFoundries, Essex Junction, VT 05452 USA. A. Bellaouar is with GlobalFoundries Austin, TX 78735 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2017.2776838 I. I NTRODUCTION T HE FinFET-based logic process technologies have been successfully put into production due to superior scalability, low-power, and high-performance benefits at 14-nm and 16-nm nodes [1]–[3]. With larger component counts in long-term evolution (LTE) phones and emerging sub-6-GHz 5G bands, area scaling is extremely important to accommodate all chipsets within cellphone from factors along with power scaling. Developing RF and analog capability of the FinFET tech- nology will help in realizing RF + Logic system on chip (SoC) to take advantage of logic power, performance, and area scaling of the advanced FinFET technology [4], [5]. Since design compatibility and low cost are important considerations for migration from the prior planar technology nodes, it is also critical in this paper to consider these factors while developing analog and RF capability in the FinFET technolo- gies. On the other hand, an increasing rate of replacing the analog circuit functions using digitally assisted analog designs favor the 14-nm FinFET technology for its scaled footprint and existing rich digital design portfolio [6], [7]. Therefore, 14-nm FinFET-based optimized RF SoC designs are an attrac- tive choice for designers in the <6-GHz RF application space. II. 14- NM RF TECHNOLOGY FEATURES The 14-nm analog and RF technology is an extension of 14-nm based logic FinFET platform technology with V dd (operational voltage) of 0.8 V for core (thin oxide) and 1.2, 1.5, and 1.8 V of input–output (I/O) (thick oxide) RF transis- tors. Table I shows a comparison of key device parameters of 14-nm core RF FinFET to 28-nm high-K metal gate planar [8] incumbent RF technology. The 14-nm FinFET devices show a clear benefit over 28-nm FETs in terms of drive current ( I d ) and transconductance (G m ) for a given design footprint. To understand the intrinsic performance benefits of these devices across technologies a figure-of-merit F t .G m / I d is also shown in Table I. A deep n-well process is also implemented to provide robust substrate isolation to microvolt level RF and analog signals. In this process, the deep n-well implant species go deeper into silicon compared to other n-well or p-well implants. The deep n-well junctions are formed with p-well (on upper edge of the deep n-well layer) and p-substrate (on the lower edge of the deep n-well layer) in the bulk silicon region below 0018-9383 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.