Planar Edge Schottky Barrier-Tunneling Transistors Using Epitaxial Graphene/SiC Junctions Jan Kunc, †,‡ Yike Hu, † James Palmer, † Zelei Guo, † John Hankinson, † Salah H. Gamal, § Claire Berger, †,∥ and Walt A. de Heer* ,†,§ † School of Physics, Georgia Institute of Technology, Atlanta, Georgia 30332, United States ‡ Faculty of Mathematics and Physics, Charles University, 12116 Prague, Czech Republic § Fac. Sci., Dept. Phys., KAU, Jeddah 21589, Saudi Arabia ∥ Institut Né el, Universite ́ Grenoble Alpes-CNRS, BP166, 38042 Grenoble Cedex 9, France * S Supporting Information ABSTRACT: A purely planar graphene/SiC field effect transistor is presented here. The horizontal current flow over one-dimensional tunneling barrier between planar graphene contact and coplanar two-dimensional SiC channel exhibits superior on/off ratio compared to conventional transistors employing vertical electron transport. Multilayer epitaxial graphene (MEG) grown on SiC(0001̅) was adopted as the transistor source and drain. The channel is formed by the accumulation layer at the interface of semi-insulating SiC and a surface silicate that forms after high vacuum high temperature annealing. Electronic bands between the graphene edge and SiC accumulation layer form a thin Schottky barrier, which is dominated by tunneling at low temperatures. A thermionic emission prevails over tunneling at high temperatures. We show that neglecting tunneling effectively causes the temperature dependence of the Schottky barrier height. The channel can support current densities up to 35 A/m. KEYWORDS: Epitaxial graphene, semi-insulating silicon carbide, Schottky barrier transistor, space-charge-limited current, tunneling field effect transistor G raphene has been widely considered as a candidate for next generation electronics due to its exceptional electronic, mechanical, and optical properties. 1,2 Logic tran- sistors 3 and high frequency transistors 4,5 have been demon- strated using the high electron mobility in graphene. However, the fact that graphene lacks band gap presents an obstacle to achieve large on/off ratio. Many efforts, such as quantum confinement, 6 applying a perpendicular electrical field, 7 and chemical functionalization, 8 have been made to open a band gap in graphene, but it is difficult to maintain high mobility while converting graphene into a semiconductor. Alternative approaches including vertical tunneling transistor structures, 9 graphene/semiconductor MESFETs, 10 and graphene Schottky barrier diodes 11 have been explored and shown significant improvement in the current on/off ratio. Solid state three- terminal devices that mimic the performance of triodes by tuning Fermi level in graphene have been also investigated. 12 Epitaxial graphene on the C-face of semi-insulating SiC has a unique advantage for the integration of graphene electronics and SiC semiconducting properties. 13 C-face multilayer epitaxial graphene can withstand high temperatures and is a very good conductor. 14 Wide band gap SiC has also attracted increasing attention due to its high breakdown field, high thermal conductivity, and high saturation drift velocity, 15 and the SiC MOSFET is considered as a promising candidate for low-loss and fast power devices. 16 C-face SiC develops into a variety of surface reconstructions upon high temperature annealing, 17,18 which can be used to tailor properties of SiC/ graphene or SiC/oxide interface. In this letter, we present fabrication and operation of a Schottky barrier transistor, which combines advantages of both graphene and SiC. The transistor exhibits up to 2 orders of magnitude higher on/off ratio than the most recent field effect transistors 10 and triodes. 12 We use semi-insulating 6H-SiC substrate (from II−VI incorporated, vanadium doped) and confinement controlled sublimation growth and annealing method. 19 A graphene-SiC-graphene Schottky barrier transistor structure is sketched in Figure 1d. It was fabricated by multiple e-beam lithography patterning, oxygen plasma etching, and two high temperature annealing steps as described below; see Supporting Information for details. A MEG is grown during the first annealing step. Then source and drain contacts are defined lithographically, followed by the conduction channel formation by high quality SiC/silicate interface at the second high temperature annealing. The sample surface has been oxygen etched everywhere except for the channel in order to avoid Received: June 3, 2014 Revised: July 9, 2014 Letter pubs.acs.org/NanoLett © XXXX American Chemical Society A dx.doi.org/10.1021/nl502069d | Nano Lett. XXXX, XXX, XXX−XXX