IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 12, DECEMBER 2013 4065 Part II: Investigation of Subthreshold Swing in Line Tunnel FETs Using Bias Stress Measurements Amey M. Walke, Student Member, IEEE, Anne Vandooren, Ben Kaczer, Anne S. Verhulst, Rita Rooyackers, Eddy Simoen, Marc M. Heyns, V. Ramgopal Rao, Senior Member, IEEE, Guido Groeseneken, Fellow, IEEE , Nadine Collaert, and Aaron Voon-Yew Thean Abstract—The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experi- ments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H + species released from the Si/SiO 2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H + species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semi- conductor trap density will be required to achieve sub-60-mV/ decade SS in line TFETs. Index Terms— Bias stress measurements, bulk traps, char- acterization, fabrication, interface traps, line tunnel field- effect transistors (TFET), subthreshold swing (SS) degradation, trap-assisted tunneling (TAT), tunnel FET (TFET). I. I NTRODUCTION B AND-TO-BAND tunneling (BTBT)-based carrier injec- tion devices have attracted much attention of the research Manuscript received July 8, 2013; revised August 27, 2013 and October 1, 2013; accepted October 15, 2013. Date of publication November 8, 2013; date of current version November 20, 2013. This work was supported by the Interuniversity Microelectronics Centre Industrial Affiliation Program. The review of this paper was arranged by Editor H. Jaouen. A. M. Walke is with the Interuniversity Microelectronics Centre, Leuven 3001, Belgium, and also with the Center of Excellence in Nano Technology, Department of Electrical Engineering Indian Institute of Technology, Mumbai 400071, India (e-mail: ameywalke@ee.iitb.ac.in). A. Vandooren, B. Kaczer, A. S. Verhulst, R. Rooyackers, E. Simoen, N. Collaert, and A. Y. V. Thean are with the Interuniversity Microelectronics Centre, Leuven 3001, Belgium (e-mail: anne.vandooren@imec.be; kaczer@ imec.be; anne.verhulst@imec.be; rita.rooyackers@imec.be; simoen@imec.be; nadine.collaert@imec.be; aaron.thean@imec.be). M. M. Heyns is with the Interuniversity Microelectronics Centre, Leuven 3001, Belgium, and also also with the Department of Metallurgy and Materials Engineering, Katholieke Universitet Leuven, Leuven 3001, Belgium (e-mail: marc.heyns@imec.be). V. R. Rao is with the Center of Excellence in Nano Technology, Department of Electrical Engineering Indian Institute of Technology, Mumbai 400071, India (e-mail: rrao@ee.iitb.ac.in). G. Groeseneken is with the Interuniversity Microelectronics Centre, Leu- ven 3001, Belgium, and also with the Department of Electrical Engi- neering, Katholieke Universitet Leuven, Leuven 3001, Belgium (e-mail: guido.groeseneken@imec.be). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2013.2287253 community due to its promise of scaling of the power supply voltage [1], [2]. At the core of these devices, popularly known as tunnel field-effect transistors (TFETs), there is a gated p + -i-n + diode operating in reverse bias [3]–[19]. Theoretically, the BTBT mechanism in TFETs can offer a subthreshold swing (SS) steeper than 60 mV/decade. However, in practice, it is very difficult to obtain a sub-60-mV/decade SS at room tem- perature due to the undesirable trap-assisted tunneling (TAT) mechanism observed in the OFF-state [3]–[15]. In an attempt to improve the ON-current and SS, a new class of devices has been discussed in the literature wherein the direction of tunneling is aligned with the gate electric field [11]–[19]. An overlap of gate with the source is a common feature of these devices. Since the ON-current is proportional to the gate length, these devices are referred to as line TFETs in this paper. Ideally, these devices are capable of providing steeper SS than a conventional gated p + -i-n + diode. However, the TAT process completely masks the BTBT current in the OFF-state, thereby degrading the SS. In the past, many groups have attributed the SS degradation to TAT through trap states at the gate dielectric–channel interface [7]–[12]. Through stress measurement experiments, we show that the SS degradation in the fabricated line TFETs is mainly due to TAT through the bulk semiconductor traps present in the pocket region. In this paper, degradation of the SS refers to deviation of the SS from the intrinsic BTBT value. This paper is organized as follows. In Section II, we present the device structure, the fabrication process, and the current– voltage characterization of the line TFETs. The SS degradation in line TFETs is investigated through stress experiments in Section III. We summarize our findings in Section IV. II. DEVICE FABRICATION AND CHARACTERIZATION The line TFET architecture can be found in many forms [11]–[19]. A conceptual figure of the line TFET is shown in Fig. 1(a). It consists of a thin intrinsic or counter-doped region sandwiched between the gate and the source so that under application of the gate bias, the tunneling is aligned with the gate electric field. In n-type TFETs, the application of the gate bias forms a potential well in the conduction band. This gives rise to quantized sub-band energy levels in the conduction band. Once the lowest of the conduction sub-bands in the pocket is aligned with the valence band of the source, the BTBT process starts and the device turns ON. In line TFETs, this field-induced quantum confinement (FIQC) mainly results 0018-9383 © 2013 IEEE