VOL. 4, NO. 3, MAY 2009 ISSN 1819-6608 ARPN Journal of Engineering and Applied Sciences © 2006-2009 Asian Research Publishing Network (ARPN). All rights reserved. www.arpnjournals.com EVALUATION OF SUBSTRATE AND WELL DOPING LEVELS AND CHIP DIMENSIONS TO PREVENT LATCH-UP IN CMOS INVERTER CIRCUITS IN SILICON USING P-WELL TECHNOLOGY WITH LINE GEOMETRY OF 0.5 µm A. K. Chatterjee 1 and Munish Vashishath 2 1 Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, India 2 Department of Electrical and Electronics Engineering, YMCA Institute of Engineering, Faridabad, India E-Mail: munish276@yahoo.com ABSTRACT CMOS inverter circuits in silicon employing p-well technology have a low current consumption in both the on and off states. However, the inherent and undesirable parasitic bipolar transistors give rise to latch-up which results in a large current flow through the chip. Based on the equivalent circuit of the parasitic transistors, it can be shown that latch-up can be shown that latch up can be prevented using a suitable substrate and well dopings. In this paper an analytical study has been made and optimum substrate and well dopings have been evaluated with (W/L) ratio ranging from 2 to 0.05 for both p-n-p and n-p-n transistors. It is expected that both substrate and well dopings of 10 15 /cc will help to solve the latch up problem for (W/L) ratio of 1. Keywords: CMOS inverter circuit, doping levels, chip dimensions. INTRODUCTION CMOS inverter circuits have been in use for quite sometime now and serve as the basic element of CMOS logic operations. These circuits have the major advantage of using a small chip area as compared to BJT based similar circuits and have significantly low power consumption in both the on and off states [1]. Normally on chip fabrication of the CMOS circuits require the use of well technology using either (1) p-well, (2) n-well or (3) twin-tub structures. However, these structures form undesirable and in-built bipolar p-n-p and n-p-n parasitic transistors which give rise to latch up causing a large current to flow from the drain supply voltage V DD to ground. The problem of latch-up technology has been solved by using the Refilled Trench Technology, whereas the p and n, twin tubes are separated by the trench [2] and the parasitic transistors become isolated from each other. These technologies require additional processing steps and are expansive. Another way to reduce the latch is to use a heavily doped substrate with devices fabricated on a highly doped epitaxial layer [3-8]. Other techniques involve the use of retrograde wells and can reduce the current gain of vertical transistors, thereby preventing latch up to occur [9-12]. In this paper an attempt has been made to reduce the current gain of the vertical and lateral parasitic transistors and solve the problem of latch-up. This has been done by estimating the current gain of the two transistors by changing the substrate and well doping such that they do not fill the condition necessary for latch-up using the equivalent circuit of the parasitic regions which involve the p-n-p and n-p-n transistor and the substrate and well resistances, R S and R W respectively. It is estimated that latch-up can be avoided by using a substrate and well doping of the order of 10 15 atoms per cc. CIRCUIT EVALUATION The circuit diagram of a CMOS inverter circuit is shown in Figure-1. The notations S 1 , G 1 , and D 1 have been used to denote the source, gate and drain of the p channel MOSFET. The subscript 2 is used for the n- channel MOSFET. The gates of the two transistors are shorted and provide the input terminal. The drains are shorted and act as the output terminal. The sources and substrate of the p-MOSFET are shorted and connected to the drain bias, V DD . Likewise the source and substrate of the n-MOSFET are shorted and connected to the source supply (-V ss ). Figure-2 shows the layered structure of a fully fabricated CMOS inverter circuit of Figure-1 using the p well structure in a silicon wafer. The symbols and notations are the same as in Figure-1. The parasitic transistors are: (1) the lateral p-n-p transistor is formed by the p + - source as emitter, n-substrate as base and p-well as the collector; (2) The vertical n-p-n transistor is formed by the n + -source (S 2 ) as emitter, p-well as the base and n substrate as the collector. The two transistors are interconnected as shown in Figure-2. The other two parasitic elements are the substrate resistance R s and the well resistance R w . The equivalent circuit of the system is shown in Figure-3. Here I rs and I rw are the currents flowing through the substrate and the well as shown in Figure-2. The current gains of the two transistors are denoted by α pnp and α npn . The other currents in Figure-3 are I, I 1and I 2 . The drain Supply voltage is (+V DD ) and source supply voltage is (-Vss). Using basic circuit theory it can be shown from Figure-3, that the current I flowing into the emitter of the p-n-p transistor can be given by: 95