A New Hybrid Topology for Network on Chip Mohammad Tahghighi*, Mahsa Mousavi**, Pejman Khadivi*** Electrical and Computer Engineering Department, Isfahan University of Technology Isfahan, Iran {M.Tahghighi*,Mh.Mousavi**,PKhadivi***}@ec.iut.ac.ir Kia Bazargan Electrical and Computer Engineering Department, University of Minnesota Minneapolis, MN, USA Kia@umn.edu Abstract—With the advancements in semiconductor chip manufacturing technology, it has been possible to put the various components of a system with more than one hundred processors, on a single chip. Network on chip (NoC) has been used as an effective communication platform for such systems. Due to the delays induced by routers and other equipment employed in NoC, the performance of communications for chips using this architecture is usually less than that of bus based versions. It is expected that a combined solution can provide benefits of both. In this paper, with the goal of reducing delays associated with on-chip communications, five new hybrid topologies have been proposed. Then, a dominant topology has been selected among the candidates and a method for routing, based on dominant topology, has been provided. Simulation results are presented to evaluate the proposed methods. Keywords-Hybrid Topology, Network on Chip, Bus, Simple Mesh, Routing algorithms for NoC. I. INTRODUCTION With the possibility of manufacturing very small semiconductor devices, placing the various components of a system with hundreds of different modules on a chip is now possible. Network on chip (NoC) is a new structure for on chip communication in such systems [1]. Network on chip is established by a series of routers which are connected by a communication channel. Each router is connected to a module (CPU, memory, etc.) and both of them are located in an area called Tile. Scalability, modularity and parallelism capability are important features of network on chip that made it a promising solution for the on chip communications [2-5]. Employment of an appropriate topology is an important issue in designing NoCs which have many effects on their performance. Topology design refers to finding the appropriate location for routers, tiles, and communication channels and to determine the associated relationships [6] and [7]. NoCs demonstrate high efficiency for huge systems, especially in point to point communications. One constraint of network on chip is its devotion to point to point communications. This is comparable with the broadcast nature of bus. In other words, multi-cast and broadcast communications show better performance in bus-based systems than the systems based on NoCs. Furthermore, using bus for a relatively small number of processing units is more appropriate because of less delay and less power consumption. Besides these features, bus based architectures are not extendable, which is one of the basic features of networks on chip. Briefly, both of NoC and bus architectures have different advantages and weaknesses. Therefore, a combined structure may come with the benefits of both of them [8-14]. In this paper, we propose a new hybrid topology that is composed of two parts: first, using bus for communication between neighbored modules and second, network on chip with capability of point to point communications. Using the locality ratio of each application, the processors which communicate more often are connected to the same bus. Therefore, the delay and power consumption is reduced in local communications. Moreover, bus is used in public communications and it can improve the speed of such communications by reducing the number of hops between two processing units which are far from each other. Bus can also provide the possibility of broadcast communications. In the topology provided in this paper, buses are arranged so that, the routes with the minimum number of hops can be created between source and destination processors. The proposed topologies can be expanded to larger sizes of network on chips. In order to use the functionalities of the proposed topologies, an effective routing algorithm is also provided so that, buses can be used in global and local communications. Hence, most of the applications can employ these topologies very effectively. The paper is organized as follows: In Section II, a brief overview of similar works is presented. Section III is about our motivations for this work and our assumptions. Section IV, introduces the new topologies and chooses the best of them. Section V is devoted to the simulation results and finally we conclude the paper in Section VI. II. RELATED WORK In the literature, different hybrid topologies are proposed for NoCs [8-14]. In this section, some relevant works are reviewed. In [8] a hybrid topology has been presented. In this topology, point to point communications are accomplished through the NoC, while public communications, control communications and time-sensitive ones are performed through bus. In the hybrid topology of [9] the possibility of creating bus for more relevant processors has been provided in the corners of the topology. In this topology, processors which are not connected to the bus can communicate through the NoC. 769 ﻣﺘﻠﺐ ﺳﺎﯾﺖ MatlabSite.com MatlabSite.com ﻣﺘﻠﺐ ﺳﺎﯾﺖ