222 PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 85 NR 10/2009 Dmitri VINNIKOV, Viktor BOLGOV Tallinn University of Technology Interlock Delay Time and its Influence on the Operability and Efficiency of High-Power DC/DC Converters Abstract. In DC/DC power converters the interlock delay time between IGBT switching on and off in the opposite inverter arms is usually recommended to be 10-20% of the half period to avoid a short circuit in a DC-link. However, in power supplies with extended input voltage variations, much smaller interlock delay time could be used. In this paper the interlock delay time minimization possibility is analyzed on an example of an experimental DC/DC converter with 6.5 kV IGBTs. The possible impact on the converter’s components, operability and efficiency are evaluated. Streszczenie. W celu uniknięcia zwarcia obwodu DC w przekształtnikach DC/DC stosuje się zwykle czas martwy równy 10-20% połowy okresu pracy. W przypadku dużej zmienności napięcia wejściowego wymagane są znacznie krótsze czasy martwe. W artykule przedstawiono analizę minimalizacji czasu martwego oraz wyniki laboratoryjne z przekształtnikiem DC/DC z tranzystorami IGBT 6,5 kV. Zbadano możliwy wpływ minimalizacji czasów martwych na podzespoły przekształtnika, możliwość jego pracy i sprawność.(Czas martwy i jego wpływ na funkcjonalność i sprawność przekształtników DC/DC dużej mocy) Keywords: DC/DC power conversion, interlock delay time, IGBT, pulse width modulated power converters. Słowa kluczowe: przekształtniki DC/DC, czas martwy, IGBT, przekształtniki z modulacją impulsową. Introduction Selection of a proper interlock delay time for a voltage source inverter with IGBTs is one of the first steps an engineer must take when starting to design a switch mode power converter. Too long interlock delay time may lead to higher filtering inductances and increased semiconductor losses. Too small interlock delay can cause the shoot trough of inverter bridge arms, input voltage distortion, shortened lifespan of transistors, and even a failure of semiconductor switching devices. Theoretically, the minimum interlock delay time between switching different inverter arm transistors on and off is the maximum control signal propagation delay from the control system to the IGBT plus time that an IGBT needs to turn on or off. There are many papers devoted to the interlock delay time analysis in AC/AC and DC/AC converters that produce modulated multiphase output [1], [2], but the problems related to the selection of a proper interlock delay time in transformer isolated DC/DC converters with non-modulated inverter output voltage are a topic of much less coverage. Several power electronics handbooks [3], [4] propose a 10- 20% interlock delay time of half period but in most cases this number could be further minimized to provide some additional benefits. This paper studies an interlock delay time minimization possibility in the half-bridge isolated DC/DC converter (Fig. 1) with high-voltage (HV) IBGTs. Fig. 1. Power circuit layout of the experimental setup The various delay times were evaluated on the simulation models that are based on the data of the experimental setup [5] with FZ200R65KF1 transistors (Infineon) and 1SD210F2 HV IGBT driver circuits (CT- concept). The control of HV IGBTs is performed by the microcontroller XC167 from Phytec. PWM signals from the control system are transferred to the high-voltage IGBT drivers via optical fibers to provide the demanded isolation barrier (12 kV). Technical specifications of the experimental setup are presented in Table 1. Table 1. Technical specifications of the experimental converter Long-term minimal input voltage U in,min , kV 2.2 Long-term maximal input voltage U in,max , kV 4.0 Nominal input voltage U in , kV 3.1 Desired output power P out , kW 50 Switching frequency f sw , kHz 1 Converter output voltage U out , kV 0.35 Driving of IGBT transistors in the half-bridge configuration is very simple. The duty ratio of inverter switches is controlled in accordance with the input voltage (Fig. 2). The most challenging operation point of the converter is at the minimum input voltage, when the switch on-state time becomes maximal. Here, the threat related to the cross conduction of top and bottom arm transistors should be considered. Fig. 2. Timing diagrams of a half-bridge inverter