Reviving Erroneous Stability-based Clock-Gating using Partial Max-SAT Bao Le 1 , Dipanjan Sengupta 1 , Andreas Veneris 1,2 Abstract—The conflicting yet increasing demand for high performance and low power in multi-functional chips has pushed techniques for power reduction to the forefront of VLSI design. Although recent developments have automated most of the low power implementations, designers often manually modify the circuit in order to achieve further power savings. This human intervention is often paved with many errors that are bound to typical logic functional failures. Debugging these errors can be a resource intensive process that requires considerable manual effort. This discourages engineers and achieving power savings at the micro level of the design sometimes remains unrealized. This paper proposes a novel debugging methodology to rectify erroneous clock-gating implementations. With the use of Partial Max-SAT, the method localizes and rectifies the design error introduced in the circuit during a clock-gating implementation. The net effect of the proposed methodology leads to shorter debug time ensuring additional power savings. Extensive experiments on benchmark circuits confirm the effectiveness of the approach. Index Terms—Debugging, Design Errors, Low Power design, Clock Gating, Stability Condition, Max-SAT I. I NTRODUCTION As low-power implementation is ubiquitous in modern VLSI chip design, designers are under immense pressure to adopt aggressive power-saving techniques. Although progress has been made in au- tomating such implementations, significant manual effort is still required to realize savings. Due to inherent design complexity and the human factor, power-saving methods can introduce design errors. When such errors occur, debugging the design to identify the root cause of failure is an overwhelming and time-consuming process. Consequently, designers often get discouraged and fail to maximize power-savings. Clock gating [1] is a circuit transformation where the clock input of a register no longer latches in new value but instead holds its current value. This enables power savings as unnecessary switching of gates can be avoided. The enable/control signal to stop the clock is computed in two phases. First, coarse-grained clock-gating is implemented by identifying the idle condition for major functional unit(s) of the design. Next, fine-grained clock-gating is inserted in register(s) by identifying idle conditions that are not visible at the architectural level. For any register in the circuit, fine-grained clock-gating takes place under the following two situations: 1) the output of the register is not observed at the primary outputs, also known as an Observability Don’t Care (ODC) [2] condition, or 2) the output of the register retains the same logic value for two or more consecutive clock cycles, a situation widely known as a Stability condition (STC) [3]. ODC is a well-studied combinational technique, studied extensively and automatically extracted from steering logic such as multiplexers, tri- state buffers and enable states [2]. In contrast, STC is a sequential technique that must be extracted from the finite state machine of the circuit and thus is much more challenging. Moreover, computing the exact STC is a resource intensive process [3]. Although [4]–[7] attempts to find these conditions automatically in any design, it is much easier for designers, having a detailed understanding of the circuit, to extract the STC and implement it manually for a particular 1 University of Toronto, ECE Department, Toronto, ON M5S 3G4 ({lebao, dipanjan, veneris}@eecg.toronto.edu) 2 University of Toronto, CS Department, Toronto, ON M5S 3G4 register. Evidently, this process is susceptible to design errors. For this reason, in the remainder of this paper, we focus on debugging fine-grained clock-gating under STC. STC is implemented by replacing the clock input of the gated register(s) by a new enable signal. The logic used to realize this enable is termed as clock-gating cone (CGC). During this process, it is often the case that existing combinational logic must also be modified to achieve the power saving transformation. Functional correctness of the clock-gated circuit is ensured by using Sequential Equivalence Checking (SEC) and/or simulation-based verification approaches. If the verification step detects the presence of design error(s), it returns a counter-example such that at least one output of the clock-gated circuit differs from the expected value for the same input vector. In such a situation today, the root cause of the failure is identified and rectified manually. With increasing design complexity and stringent time-to-market windows, finding such design errors becomes an arduous task. As such, it is common practice for some of the clock-gating implementations to be discarded leading to reduced power savings to what ideally one may be able to achieve. This work proposes a novel debug strategy for erroneous clock- gating implementations under fine-grained STC. The first step is a light weight checking technique for identifying the relative location of the design error. In this step, the erroneous clock-gated circuit is transformed to a modified circuit that is used to quickly provide an insight to the location of the error - namely the CGC and/or the modified combinational logic. Next, a Partial Max-SAT solver utilizes this localization by the pre-processing step to iteratively identify the set of erroneous gates that may be responsible for the logic failure. Once the set of possible erroneous gates have been identified, a gate- level rectification methodology is devised to correct the error. As a result of the above debug and rectification procedures, more power savings can be revived in the circuit leading to increased power savings. Previous work [8], [9] focuses on reducing power in a clock-gated circuit by allowing problematic/erroneous clock-gating conditions. In [9] the error effects are canceled out before being observed at the primary output by injecting new clock-gating conditions. In [8], problematic clock-gating conditions are merged by approximation and clustering techniques. As discussed earlier, finding additional clock-gating is an extremely challenging task and merging clock- gating is a complex process, requiring deep understanding of the de- sign. In contrast, our rectification technique refrains from introducing additional clock-gating conditions as well as merging different clock- gating logic. It rather fixes the root cause of the design error. The motivation behind the proposed approach is to retain most or all of the manual modifications in the design while being able to rectify the circuit. Experiments on benchmark circuits show that our proposed method is more robust and the pre-processing step leads to significant reduction in debug runtime. Moreover, 98% power savings can be regained by rectifying the erroneous CGC. The remaining paper is organized as follows. Section II discusses related work in clock-gating as well as Max-SAT approach for design debugging. Section III proposes the pre-processing step for error localization. Section IV presents the Max-SAT formulation for clock- gating debug followed by the proposed rectification methodology. Ex- perimental results are presented in Section V followed by conclusion in Section VI. II. PRELIMINARIES Given a sequential circuit C (Ca), the symbols X(Xa),Y (Ya), and S(Sa) denote the set of primary inputs (PI ), primary outputs (PO), and state elements (flip flops) respectively. The circuit is