VOL. 10, NO. 9, MAY 2015 ISSN 1819-6608 ARPN Journal of Engineering and Applied Sciences © 2006-2015 Asian Research Publishing Network (ARPN). All rights reserved. www.arpnjournals.com 4042 INPUT VECTOR MONITORING CONCURRENT BIST ARCHITECTURE USING MODIFIED SRAM CELLS B. Divyapreethi and T. Karthik VLSI Design, Karpagam College of Engineering, Coimbatore, India Department of Electronics and Communication, Karpagam College of Engineering, Coimbatore, India E-Mail: 1990divyaei@gmail.com ABSTRACT Input vector monitoring concurrent BIST performs two modes of operation, normal mode and test mode during test mode the test generator value is compared with higher order bits and the output is given to comparator circuit. During normal mode the inputs to the CUT are driven from the normal inputs. The modified SRAM is used to reduce the switching activity hence the dynamic power dissipation can be reduced. The output is verified by response verifier (RV) and the fault is identified using testing. The operating speed is faster since the operation is carried out as parallel process and it is suitable for all the type of IC’s. Keywords: comparator, test generator enable, concurrent BIST unit, modified SRAM, logic module, concurrent test, response verifier. 1. INTRODUCTION: Built-in-self test (BIST) techniques constitute a class of schemes that provide the capability of performing testing with high fault coverage. Hence, they constitute an attractive solution to the problem of testing VLSI devices. BIST techniques are typically classified into offline and online. Offline architectures operate in either normal mode (during which the BIST circuitry is idle) or test mode. During test mode, the inputs generated by a test generator module are applied to the inputs of the circuit under test (CUT) and the responses are captured into a response verifier (RV).The bits are classified into higher and lower order bits. During the normal mode the vector that drives the inputs of the CUT is driven from the normal input vector. It operates in two modes. When T/N=0 it operates in normal mode, if T/N=1 the operation is said to be in test mode. The modified decoder and the modified SRAM are used. The decoder operation is carried along with TGE and CMP values based on which the decoding operation occurs. Modified SRAM is used not only for storing purpose but also for reducing the switching activity. This leads to reduction in dynamic power dissipation. The output from both the logic circuit and the CUT are captured and it is verified using response verifier (RV). The process is carried out parallel hence speed of operation is more. 2. BLOCK DIAGRAM DESCRIPTION CBU tge w inputs k t/n cmp k w clk reset CUT MUX C O M P M‐ DEC RV LOGIC TG a) Hardware test pattern generator This module generates the test patterns required to sensitize the faults and propagate the effect to the outputs. As the test pattern generator is a circuit (not equipment) its area is limited. So storing and then generating test patterns obtained by ATPG algorithms on the CUT Using the hardware test pattern generator is not feasible. Instead, the test pattern generator is basically a type of register which generates random patterns which act as test patterns. The main emphasis of the register design is to have low area yet generate as many different patterns (from 0 to 2 n-1 , if there are n flip-flops in the register) as possible. b) Decoder A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input