IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 2, FEBRUARY 2009 189 Gate-Induced Drain-Leakage (GIDL) Programming Method for Soft-Programming-Free Operation in Unified RAM (URAM) Jin-Woo Han, Seong-Wan Ryu, Sung-Jin Choi, and Yang-Kyu Choi Abstract—A soft-programming-free operation method in uni- fied RAM (URAM) is presented. An oxide/nitride/oxide (O/N/O) layer and a floating-body are integrated in a FinFET, thereby providing the versatile functions of a high-speed capacitorless 1T-DRAM, as well as nonvolatile memory, and the mode of the memory cell can be selected and independently utilized according to the designer’s demand. With the utilization of the impact ionization method for 1T-DRAM programming, undesired soft charge trapping into O/N/O gradually shifts the threshold voltage, resulting in an unstable operation in the URAM. In order to avoid such problems associated with soft programming, a gate-induced drain-leakage (GIDL) program method is proposed for improved immunity to disturbance. It is found that the GIDL method effec- tively suppresses soft programming without sacrificing the sensing current window. Index Terms—Disturbance, FinFET, gate-induced drain leak- age (GIDL), nonvolatile memory (NVM), soft program, SONOS, unified RAM (URAM), 1T-DRAM. I. I NTRODUCTION H IGH-SPEED 1T-DRAM and nonvolatile Flash memory have been integrated into a single memory cell transistor, thus realizing the so-called unified RAM (URAM), in order to provide versatile memory applications for embedded systems [1], [2]. By combining an oxide/nitride/oxide (O/N/O) gate dielectric as an electron-trapping layer for Flash memory and a partially depleted floating-body as a hole-storage region for 1T-DRAM, URAM operation has been realized in a single memory transistor. Unfortunately, impact ionization for pro- gramming of the 1T-DRAM mode can adversely affect trapped charges in the O/N/O layer. Whereas a faster writing speed of 1T-DRAM requires harsh impact ionization conditions, in- creased impact ionization current causes hot electron injec- tion into the O/N/O layer, resulting in the threshold voltage shift after cyclic 1T-DRAM operations. Therefore, the program voltage of the 1T-DRAM mode becomes restricted as low as Manuscript received October 9, 2008; revised November 18, 2008. First published December 31, 2008; current version published January 28, 2009. This work was supported in part by the National Research Program for the 0.1-Terabit Nonvolatile Memory Development, sponsored by the Ministry of Knowledge Economy. The review of this letter was arranged by Editor T. Wang. The authors are with the Division of Electrical Engineering, School of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail: jinu0707@nobelab. kaist.ac.kr; siege0@nobelab.kaist.ac.kr; sjchoi@nobelab.kaist.ac.kr; ykchoi@ ee.kaist.ac.kr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2008.2010345 Fig. 1. Schematics of excess-hole-generation method for capacitorless 1T-DRAM. (a) Impact ionization. (b) Band-to-band tunneling (GIDL). Whereas created electrons can be injected into the gate dielectric, created holes are restricted for injection due to the large effective mass and higher valence- band barrier. possible so as not to disturb the nonvolatile memory (NVM) state. As such, development of a disturbance-free programming method is essential for reliable URAM operation. A capacitorless 1T-DRAM using gate-induced drain-leakage (GIDL) current has been presented for low-power and high- speed memory [3]. Unlike impact ionization, the GIDL method does not involve hot electron injection, and it generates an excessive amount of holes in the floating-body. As shown in Fig. 1, a device biased on the GIDL condition, i.e., a negative gate voltage and a positive drain voltage, creates excessive holes in the channel by band-to-band tunneling. Hole injection into nitride traps is restricted, however, if the NVM is in the erase state prior to the 1T-DRAM mode of URAM operation. Thus, 1T-DRAM can operate without operational interfer- ence. In this letter, GIDL current is used at the 1T-DRAM mode of URAM instead of the impact ionization current for a disturbance-free operation. The impact of the 1T-DRAM program method on soft programming is evaluated for both impact ionization and GIDL methods. Finally, a p + poly-Si gate MOSFET built on a SOI is presented as an effective means of improving the GIDL current. II. RESULTS AND DISCUSSION The URAM device structure, process flow, and electrical characteristics, including NVM and 1T-DRAM properties, can be found in [2]. The fabricated FinFET has a fin width of 30 nm, a gate length of 180 nm, an O/N/O thickness of 3/8/3 nm, and a fin height of 110 nm. While the upper 60 nm of the fin is cov- ered by the gate, the lower 50 nm is covered by SiO 2 to leave the body floating. In a previous work, all measurement tests were carried out at 25 ◦ C, and the substrate (back gate) was grounded. In order to clarify the soft-programming problem arising from 0741-3106/$25.00 © 2009 IEEE