Design of Semi-Static SET Flip-Flop for Low Power and High Performance Applications Imran Ahmed Khan*, Mirza Tariq Beg . Department of Electronics and Communication, Jamia Millia Islamia, New Delhi, India Abstract— The paper proposed a new design for implementing semi-static flip-flop for low power and high performance applications. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. The proposed design has better power, delay and PDP than the existing architectures. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that for all supply voltages, all clock frequencies and all data activities, the proposed flip-flop has the better power consumption than all the six existing flip-flops discussed in this paper. The proposed flip-flop also shows the second lowest PDP and the second shortest delay. Keywords— Single edge triggered, PDP, Energy efficient, High performance I. INTRODUCTION In CMOS digital logic design, power consumption has been a major concern for the past several years. Due to the advancement in IC fabrication technology that allows the use of nano-scale devices, the power dissipation is a prominent issue [1]. In the present design consideration the power consumption and chip area requirements are small and the operating frequency is high compared to conventional discrete I.C. design, so low power design with high performance is becoming increasingly important [2]. Flip-flops are widely used in building many sequential logic circuits such as registers, memory elements, counters, etc. These circuits are heavily used in the implementation of VLSI chips. Therefore the improvement in power consumption of such circuits, without weakening other characteristics, is of prime importance to the VLSI industry [3]. In this paper, a new architecture of single edge triggered flip-flop is proposed. The conventional and the proposed single edge triggered flip-flop are presented and compared. The superior performance of the proposed work has been pointed out, providing high frequencies across supply voltages. For all circuits, simulations are carried on 130nm process node using BSIM3 models. This paper is organized into six sections. Section II compares the existing single edge triggered flip-flop structures. In section III, a new flip-flop structure is proposed. The nominal simulation conditions, along with analysis and optimization performed during simulation, are discussed in section IV. In section V results are presented and proposed design is compared with conventional designs in terms of power, delay, PDP and transistor count. Section VI ends the paper with conclusion. II. EXISTING SINGLE EDGE TRIGGERED FLIP-FLOPS The static Push Pull Flip-Flop (PPFF) is shown in Fig. 2. To improve the performance of a conventional Transmission Gate Flip-Flop (TGFF shown in Fig. 1) [4], [5], addition of an inverter and transmission gate between the outputs of master and slave latches to accomplish a push–pull effect at the slave latch, was proposed in [6]. This increased 4 transistors. To compensate this increment of transistor count, two transmission gates are eliminated in the Push Pull Flip-Flop from the feedback paths of conventional TGFF. Fig. 3 shows the static C 2 MOS Flip- Flop [7]. This flip-flop consists of a C 2 MOS feedback at the outputs of the master and the slave latches. When clock is at logic ‘HIGH’, the clocked inverter CLKI1 latches the input D to an intermediate node N. The feedback consisting of clocked inverter CLKI2 and inverter I1 maintains this logic level at node N when clock is at logic level ‘HIGH’. Similarly when CLK changes to logic ‘LOW’, the slave latch gets functional and clocked inverter CLKI3 transfers the logic level from node N to the output Q. The feedback consisting of clocked inverter CLKI4 and inverter I2 maintains this logic level at output node Q when clock is grounded. There are 20 transistors in this circuit. So C 2 MOSFF has largest area but this flip-flop shows the shortest delay and the lowest PDP. The Area Efficient flip-flop was proposed in [8]. This semi-static flip-flop is illustrated in Fig. 4. This flip-flop has lesser transistor count as compared to above discussed flip-flops. In this design the feedback circuit of the master section is removed and in slave section, feedback loop consists of a transmission gate. When clock level is ‘HIGH’, master latch is functional and inverse of the data is stored to an intermediate node N. When clock goes to ‘LOW’ logic level, the slave latch becomes functional and produces data at the output Q and QB. In High Performance Flip-Flop (HPFF), a feedback is provided from the output node of the slave inverter to a specific internal node in the master-stage as shown in Fig. 5. This flip-flop was proposed by [9]. This feedback is provided by only a single transistor. So this has lesser number of transistor as compare to other flip flops. The main advantage of this design is reduced device count and decreased parasitic capacitance at internal nodes of the flip flop which results in improved power-delay product. To save power, the number of transistors of the proposed flip-flop was reduced in [10]. The four transistors in the feedback path of conventional TGFF are replaced by single PMOS transistor. Hence, total 6 transistors are reduced Imran Ahmed Khan et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 5 (1) , 2014, 284-289 www.ijcsit.com 284