ELECTRON TRAPPING: AN UNEXPECTED MECHANISM OF NBTI AND ITS IMPLICATIONS J.P. Campbell 1 *, K.P. Cheung 1 , J.S. Suehle 1 , A. Oates 2 1 Semiconductor Electronics Division, NIST, Gaithersburg, MD 20899, 301-975-8308, *email: jason.campbell@nist.gov 2 TSMC Ltd. No. 121, Park Ave. 3, Science-Based Industrial Park, Hsin-Chu, Taiwan 300-77, R.O.C INTRODUCTION NBTI is the most important reliability problem in advanced CMOS technology.[1] Consequently, the recent CMOS reliability literature is dominated by the characterization and modeling of NBTI. All of the existing literature attributes the NBTI-induced ΔV TH and I D degradation to interface state generation and/or hole trapping.[2] In this work, we demonstrate that electron trapping has been overlooked in previous studies and will greatly impact the current understanding of the NBTI phenomenon and consequent lifetime predictions. KEY RESULT The key experimental evidence demonstrating electron trapping during NBTI is shown in figure 1 which illustrates the %peak-G M degradation as a function of recovery time. 1.6nm SiON pMOSFETs were subjected to an NBTI stress of -2.5V/125C/10secs. Figure 2 illustrates our measurement sequence in which an I d V g measurement is taken on the rising edge (pre-stress) and falling edge (post-stress) of the gate pulse as well as after a variable recovery period (post- recovery). Each data point represents an average of 12 measurements and a fresh device is used for each recovery time. The pre- stress/post-stress or “zero–recovery” %G M degradations are shown in figure 1 for reference. Demonstration of electron trapping is found from a comparison of the pre-stress/post-recovery or “recoverable” data which is clearly dependent on the recovery time. Significant G M degradation is clearly evident at the shortest recovery time (2 μsecs). However, as the recovery time increases, the G M degradation clearly reduces and crosses over to G M values greater than before stress (negative values on figure 1). At longer recovery times, the G M values return to the degraded state. This G M behavior has never been reported since G M extraction is usually difficult to obtain from fast- I d V g measurements. The full G M curves are shown in figure 3 for the G M degradation (fig. 3(a)) and G M improvement (fig. 3(b)) cases. The observed G M behavior can be explained by hole as well as electron trapping and detrapping. Although our stress condition is rather common for NBTI studies of ultra thin gate dielectrics, it represents an electric field that is traditionally categorized as high- field stressing. Under high-field stress, it is known [3] that both electron- and hole-trapping occurs. It is also known that both electrons and holes will detrap once the stress is removed, but with very different detrapping rates (with holes detrapping faster).[4] At the conclusion of stress, both trapped holes and trapped electrons are present, along with positively charged interface states (I-V measurement condition) and we observe a maximum G M degradation. As the recovery time increases, the much higher rate of hole-detrapping leads to a decrease in net trapped charge (bulk plus interface) as well as Coulombic scattering. Thus, the measured G M degradation is reduced. This continues until the trapped holes in the bulk are largely depleted and electron-detrapping has a stronger impact on the net charge in the bulk. At this point the net charge in the bulk is negative and it is over compensating the positive interface charges added by the stress, leading to G M improvement. At longer recovery times, electron detrapping continues and the net negative charge in the dielectric diminishes. This leaves only the positive interface state charge and the G M returns to degradation. EXPERIMENTAL Fully processed 2 x 0.07μm 2 and 2 x 0.06μm 2 (physical gate area) SiON pMOSFETs (T ox = 1.6nm) were used in this work. Our fast- I d V g measurement (2 digital oscilloscopes, 2 pulse generators, and a fast amplifier circuit)is capable of ≈ 2 μsec measurement time. The unique capability that enables this work is the ability to perform stress over a time scale from microseconds to essentially infinite time while maintaining the ability of controlling the recovery time to better than a microsecond. Figures 4(a) and 4(b) illustrate the very good agreement between the raw and filtered data from our fast-I d V g measurement and the DC measurement using a parametric analyzer. Figure 4(c) illustrates the extracted G m characteristic from the fast- I d V g measurement which also shows very good agreement with the DC-measurement. It is important to note that the effect of electron trapping can only be seen with a sufficiently fast I d V g measurement. Figure 5 illustrates the measured recoverable (-2.5/125C/10sec) %G M degradation as a function of measurement time (rise/fall time of the gate pulse) for several different recovery times. It is clear that the measurement time must be less than 10usecs to observe the aforementioned G M trends. It is also clear, that the recovery time greatly alters the result as the 10μsec recovery time exhibits a G M degradation while the 100msec and 10sec recovery times exhibit a G M improvement (negative values in figure 5). RESULTS AND DISCUSSION One would expect the hole and electron detrapping phenomenon which is affecting the G M characteristics to also be reflected in the ΔV TH measurement. However, we find that this trend is much harder to observe in the ΔV TH measurements (figure 6) that were extracted from the same I d V g measurements used to produce figure 1 (linear extrapolation at max G M ). This is because this stress conditions results in a relatively small ΔV TH which is overwhelmed by the error of the measurement. We have previously reported [5] zero-recovery and recoverable (5 seconds) ΔV TH and %G M degradations as a function of stress voltage for various stressing times at 125°C (figure 7). It is clear from these measurements that a large initial ΔV TH is only observable at exceedingly high stress voltages and long stress times. Similarly, G M improvement is easier to observe at higher stress voltages (figure 8). In an effort to correlate V TH behavior with G M , we repeated our experiment using a harsher stress condition (-2.7V/125C/1000secs). Figures 9 and 10 illustrate the zero-recovery and recoverable ΔV TH and %G M degradations as a function of recovery time for this harsher stress case. In this case, the ΔV TH trend (figure 9) mimics the G M trends as expected (fig 10). Note that both hole-detrapping and electron-detrapping rates are higher in this case which results in a G M turn around at a much earlier recovery time. Electron-detrapping is assisted by interface states via trap-to-trap tunneling. The detrapping rate increase is a result of the much higher interface state density due to the hasher stress. The higher hole-detrapping rate is the normal result of higher stress voltage [6]. The observed earlier G M turn around time thus further supports our interpretation. CONCLUSION We have clearly demonstrated for the first time that the trapping and detrapping of electrons play a major role during common NBTI stressing and recovery conditions. We also showed that both hole- detrapping and electron-detrapping rates are dependent upon the stress condition and both slow down at less severe stress conditions. Furthermore, it is known that hole-detrapping is insensitive to temperature while electron-detrapping is highly sensitive to temperature. At lower temperatures, electron detrapping can be extremely slow. These factors greatly complicate both the characterization and modeling of NBTI. These results indicate that without accounting for the electron trapping and detrapping, the life- time projection of NBTI based on the previously suggested physical models may be unreliable. 978-1-4244-1805-3/08/$25.00 © 2008 IEEE 2008 Symposium on VLSI Technology Digest of Technical Papers 76