Analysis of current collapse effect in AlGaN/GaN HEMT: Experiments and numerical simulations M. Faqir a,d , M. Bouya a,b, * , N. Malbert a , N. Labat a , D. Carisetti b , B. Lambert c , G. Verzellesi d , F. Fantini d a IMS Laboratory, Université Bordeaux 1, 351 cours de la libération, 33405 Talence Cedex, France b TRT-France-LATPI, Route départementale 128, 91767 Palaiseau Cedex, France c United Monolithic Semiconductors, Domaine de Corbeville, 91404 Orsay Cedex, France d Department of Information Engineering, University of Modena and Reggio Emilia, Modena, Italy article info Article history: Received 28 June 2010 Accepted 13 July 2010 Available online 21 August 2010 abstract In this work, current collapse effects in AlGaN/GaN HEMTs are investigated by means of measurements and two-dimensional physical simulations. According to pulsed measurements, the used devices exhibit a significant gate-lag and a less pronounced drain-lag ascribed to the presence of surface/barrier and buf- fer traps, respectively. As a matter of fact, two trap levels (0.45 eV and 0.78 eV) were extracted by trap- ping analysis based on isothermal current transient. On the other hand, 2D physical simulations suggest that the kink effect can be explained by electron trapping into barrier traps and a consequent electron emission after a certain electric-field is reached. Ó 2010 Elsevier Ltd. All rights reserved. 1. Introduction GaN based high electron mobility transistors (HEMTs) have emerged as very attractive candidates for high temperature, high-voltage, and high-power operation at microwave as well as lower frequencies [1]. Presently, demonstrating a solid reliability is, probably, the final step before AlGaN–GaN HEMTs can massively be adopted in RF power applications. The appearance and/or amplification of RF cur- rent collapse is unfortunately one of the effects that more com- monly take place during both DC [2] and RF [3] electrical stresses, even in devices that show immunity from this detrimental phenomenon before stress. On the other hand, Kink effect is detrimental for the perfor- mance of HEMTs, and can result in output-conductance increase, transconductance compression, and dispersion between dc and RF characteristics. In GaAs based FETs kink effect was ascribed either to channel impact ionization and subsequent hole accumu- lation or field-dependent trapping/detrapping in deep levels [4]. Recently, kink effects have been described in GaN HEMTs and were supposedly attributed to impact ionization and/or trapping/detrapping in buffer traps [5–8]. In spite of the ever-increasing research efforts and recent pro- gresses, a well-defined picture of the physical mechanisms limiting the reliability of GaN HEMTs is still to be achieved, so that trying to gain insight about the possible degradation effects and the under- lying mechanisms is still a worthwhile effort. In view of this, experimental measurements, as well as 2D phys- ical simulations have been carried out in the present work. The ef- fect of surface and buffer traps is shown. Furthermore, we propose for the first time, to our knowledge, a new explanation to the kink effect with the aid of 2D physical simulations. Indeed, our simula- tions suggest that barrier traps can account for kink effect, ruling out the more unlikely impact-ionization explanation (considering the wide bandgap of the involved materials and the device opera- tion conditions). 2. Experimental results The study was carried out on 0.5 lm AlGaN/GaN HEMT grown on SiC substrate. The gate is composed of eight fingers (W = 8  125 lm). The Ni/Au gate is passivated by SiN and located closer to the source than to the drain. The ohmic contacts are composed of a Ti/Al/Au/Ni stack with a Ti/Pt/Au thickening. In Fig. 1, pulsed I DS –V DS characteristics were measured using a pulse width of 500 ns. Drain current is higher for the quiescent point (V GS 0, V DS 0) of (0 V, 0 V) compared with the other ones. This result is linked with the activation of surface and/or barrier traps with time constant higher than 500 ns [9]. These traps are gener- ally assumed to induce the RF current collapse [10]. In fact, the gate-lag mechanism suggested by 2D physical simulations is basi- cally the concept of ‘‘virtual gate” formed by surface donor traps, which capture electrons injected by the gate under large and neg- ative V GS bias and emit them as V GS is switched to higher values [9]. 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.020 * Corresponding author at: IMS Laboratory, Université Bordeaux 1, 351 cours de la libération, 33405 Talence Cedex, France. E-mail address: mohsine.bouya@thalesgroup.com (M. Bouya). Microelectronics Reliability 50 (2010) 1520–1522 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel