872 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 7, JULY 1999 Express Letters Low Delta-I Noise CMOS Circuits Based on Differential Logic and Current Limiters Jose Luis Gonz´ alez and Antonio Rubio Abstract— Switching noise is becoming an important constraint in mixed signal design. In this paper we present an approach to implement combinational circuits that generate low levels of delta-I noise by obtain- ing a trapezoidal current waveform shape. We use a differential logic (ECDL) together with current limiters to implement a 4 4 multiplier. We present the results of the simulation of this multiplier and the comparison with the static complementary–metal–oxide semiconductor (CMOS) implementation. Index Terms— Digital integrated circuits, self-time logics, switching noise. I. INTRODUCTION Switching noise or Delta-I noise is becoming an important con- straint in current fast digital and mixed signal IC’s [1], [2]. The Delta-I noise is mainly due to the current demanded by the digital logic when switching. This current produces voltage spikes across bonding wires, power planes, and pin inductance. The switching noise is proportional to the effective inductance (Leff) of the power and ground distribution frame multiplied by . We can reduce this switching noise by reducing . The derivative of the current waveform is related with its shape. An isosceles-triangle-like waveform would produce a square voltage noise waveform and the noise amplitude should be proportional to the rising or falling slope. Another interesting current waveform shape is the trapezoidal. The voltage noise produced by this last current waveform shape consists of a positive voltage spike in the rising edge and a negative voltage spike in the falling edge, without voltage noise during the flat middle section of the trapezoidal-current waveform. This is the current waveform that we obtain in a long static complementary–metal–oxide semiconductor (CMOS) ring oscillator. In this paper we present a design methodology that tries to approximate the current waveform of the logic circuits to an ideal trapezoidal shape, to minimize the switching noise generated by the digital part of an IC. II. DESIGN METHODOLOGY We consider a logic circuit as an interconnection of basic logic gates or blocks. Once the inputs change, different gates switch consecutively until the final result appears in the outputs. At a given time, one or more gates could switch simultaneously. The final current waveform is the temporal overlap of the individual gates’ current waveform. The waveform shape depends on the individual current shape and amplitude of each gate, the number of simultaneous Manuscript received December 9, 1997; revised December 8, 1998. This work was supported in part by the Spanish Education and Science Ministry under Research Project TIC 95/0469. This paper was recommended by Associate Editor A. H. M. Van Roermund. The authors are with the Departament d’Enginyeria Electr` onica, Universitat Polit´ ecnica de Catalunya, 08034 Barcelona, Spain. Publisher Item Identifier S 1057-7122(99)05659-7. Fig. 1. (a) Ideal trapezoidal current waveform obtained by overlapping four individual gate currents. (b) Current limiters in the power and ground nodes of a ECDL cell. switching gates, and the switching times. We may define some conditions to assure that a trapezoidal-like waveform would be obtained, that are depicted in Fig. 1(a). 1) The number of simultaneous switching gates at a given time must always be the same. 2) The shape and amplitude of the individual current waveforms must be the same for all the different logic gates, independently of the input vector change and the gate’s logical function. These two conditions are not satisfied in a static CMOS design because the switching of a given gate depends on the input vector change (i.e., a change in the inputs of a static CMOS NAND from 00 to 11 produces a current spike, but a change from 00 to 01 does not) and the amplitude depends also on the input vector (in a static CMOS NAND the current spike in the switching produced by a 00–11 is approximately twice as large as the one corresponding to a 01–11 input change). Following the above conditions a design procedure can be highlighted as follows. 1) Make the logic circuit as regular as possible, adding redundant blocks in order to have. at a given time and for any input condition. an equal number of switching gates. 2) Use a logic that would produce current spikes of approximately the same shape and amplitude, independently of the change of the inputs and with approximately the same gate delay for any logic function and input vector. 3) The delay of each block or gate of the regular structure must be the same. If necessary, we can partition big blocks into smaller ones until we attain a spatial and temporal uniformity of the structure. Also we can insert dummy delay cells to compensate for the possible nonuniformities. 1057–7122/99$10.00  1999 IEEE