A Framework for Early and Systematic Evaluation of Design Rules Rani S. Ghaida and Puneet Gupta Electrical Engineering Dept., University of California, Los Angeles {rani,puneet}@ee.ucla.edu Abstract—Design rules have been the primary contract be- tween technology and design and are likely to remain so to preserve abstractions and productivity. While current approaches for defining design rules are largely unsystematic and empirical in nature, this paper offers a novel framework for early and systematic evaluation of design rules and layout styles in terms of major layout characteristics of area, manufacturability, and variability. Due to the focus on co-exploration in early stages of technology development, we use first order models of variability and manufacturability (instead of relying on accurate simulation) and layout topology/congestion-based area estimates (instead of explicit and slow layout generation). The framework is used to efficiently co-evaluate several debatable rules (evaluation for a 104-cell library takes 20 minutes). Results show that: a) diffusion- rounding mainly from diffusion power-straps is a dominant source of variability, b) cell-area overhead of fixed gate-pitch implementation compared to 1D-poly implementation is tolerable (5%) given the improvement in variability, and c) 1D-poly restriction, which improves manufacturability and variability, has almost no area overhead compared to 2D-poly. In addition, we explore gate-spacing rules using our evaluation framework. This exploration yields almost identical values as those of a commercial 65nm process, which serves as a validation for our approach. I. I NTRODUCTION The semiconductor industry is likely to see several radical changes in the fabrication and device technologies in the next decade. On the patterning front, disruptive changes include adoption of one or more of candidate next-generation lithog- raphy techniques such as nanoimprint, electron beam direct write, and extreme ultraviolet [1–4]. Each of these has chal- lenging implications for layout methodologies and design rules (DRs). Resolution enhancement techniques (RETs) and other patterning solutions such as immersion and double-patterning lithography (DPL), off-axis illumination (OAI), sub-resolution assist features (SRAFs), and phase-shift mask (PSM) re- quire additional layout-restrictive DRs [5–11]. Therefore, early assessment of design restrictions imposed by technological choices is absolutely essential. DRs are the biggest design-relevant quality metric for a technology. Even small changes in DRs can have significant Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ICCAD’09, November 2-5, 2009, San Jose, California USA. Copyright 2009 ACM 978-1-60558-800-1/09/11...$10.00. Figure 1: Overview-diagram of DRE framework. impact on manufacturability [12] as well as circuit charac- teristics including layout area, variability, power, and perfor- mance [13, 14]. Unfortunately, even after decades of existence, design-rule evaluation and exploration is largely unsystematic and empirical in nature. Several published works have done “one-at-a-time” evaluation of design rules empirically [12, 15]. For example, [16] evaluates line-end extension rule electrically to conclude that it may be too conservative. Other recent works [17, 18] offer solutions to explore DRs from a pure printability perspective and do not examine the effects of DRs on circuit characteristics. Moreover, none of these methods account for layout topology changes that may happen when DR values change significantly. They also ignore several prac- tical constraints imposed on layouts by the standard-cell design methodology (e.g., cell width and height being quantized). Finally, these approaches are simulation and/or explicit layout generation-based, which makes them slow and dependent on model accuracy. To the best of our knowledge, this paper proposes the first framework to explore area-manufacturability-variability tradeoffs of design rules systematically and in a quantitative manner. Rather than fine-tuning DRs, our goal is to make early decisions before exact process and design technologies are known. At this stage, accurate evaluation methods and models are unlikely to be available and the return on investment of using them is fairly low. As a result, we use simple but justified approximations for manufacturability and variability unlike [19, 20] that rely on layout generation or perturbation. Since design rule space is very large, we further use fast layout topology generation methods to estimate area as opposed to full-blown layout generation. The accuracy of the former is surprisingly good and allows for explicit “layout style”