Received February 11, 2018, accepted March 22, 2018, date of publication March 28, 2018, date of current version April 23, 2018. Digital Object Identifier 10.1109/ACCESS.2018.2820122 FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition AHMED A. HUSSAIN 1 , NIZAR TAYEM 1 , (Member, IEEE), MUHAMMAD OMAIR BUTT 1 , ABDEL-HAMID SOLIMAN 2 , ABDULRAHMAN ALHAMED 3 , AND SALEH ALSHEBEILI 3 1 Department of Electrical Engineering, Prince Mohammad Bin Fahd University, Alkhobar 31952, Saudi Arabia 2 School of Engineering, Staffordshire University, Stoke-on-Trent, ST4 2DE, U.K. 3 KACST-TIC in RF and Photonics for the e-Society (RFTONICS), Department of Electrical Engineering, King Saud University, Riyadh 11421, Saudi Arabia Corresponding author: Ahmed A. Hussain (ahussain1@pmu.edu.sa) This work was supported by the Deanship of Scientific Research at King Saud University through the Research Group under Grant RG-1438-092. ABSTRACT In this paper, authors present their work on field-programmable gate array (FPGA) hardware implementation of proposed direction of arrival estimation algorithms employing LU factorization. Both L and U matrices were considered in computing the angle estimates. Hardware implementation was done on a Virtex-5 FPGA and its experimental verification was performed using National Instruments PXI platform which provides hardware modules for data acquisition, RF down-conversion, digitization, etc. A uniform linear array consisting of four antenna elements was deployed at the receiver. LabVIEW FPGA modules with high throughput math functions were used for implementing the proposed algorithms. MATLAB simulations of the proposed algorithms were also performed to validate the efficacy of the proposed algorithms prior to hardware implementation of the same. Both MATLAB simulation and experimental verification establish the superiority of the proposed methods over existing methods reported in the literature, such as QR decomposition-based implementations. FPGA compilation results report low resource usage and faster computation time compared with the QR-based hardware implementation. Performance comparison in terms of estimation accuracy, percentage resource utilization, and processing time is also presented for different data and matrix sizes. INDEX TERMS FPGAs, LU factorization, NI PXI platform, pipelined architecture. I. INTRODUCTION With the rapid advances in the different fields of communica- tion technologies, DOA estimation finds important practical applications in areas such as channel estimation and equaliza- tion, echo and interference cancellation, source localization in radar and sonar systems, beam forming ‘smart’ adaptive antenna arrays in wireless mobile communications systems, and multiple-input-multiple-output (MIMO) systems [1]–[4]. Majority of the research work reported in these areas has focused primarily on numerical simulations of the algorithms for DOA estimation to establish their accuracy and effi- cacy [5]–[11]. However, due to the practical significance of these problems, these algorithms are required to be imple- mented and tested on real hardware to validate their viability in terms of computational speed, memory requirements, and implementation cost in hardware. In addition, most applica- tions require the DOA estimates to be computed in real-time (with computation speeds of the order of a few microseconds or even nanoseconds) such as in tracking a very fast moving target using a radar or sonar. The performance of a DOA algorithm is determined by several factors such as the size, number of elements and spac- ing of the antenna array as well as different configurations of impinging signals. Many DOA techniques exist [5]–[10], which are based on analysis of covariance matrix using Eigen Value Decomposition (EVD) or analysis of received data matrix using Singular Value Decomposition (SVD). Both EVD and SVD based algorithms involve separating noise and signal subspaces that can be used to infer angles of arrival of impinging signals. 17666 2169-3536  2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. VOLUME 6, 2018