IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 2, FEBRUARY 2013 405 Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS Pin-Hao Feng and Shen-Iuan Liu, Fellow, IEEE Abstract—Four divide-by-3 injection-locked frequency dividers (ILFDs) are fabricated in 40-nm CMOS technology. A second-har- monic peaking technique is used to enhance the locking range. The distributed inductor technique is used to enhance the operation frequency and the locking range. The locking range and design considerations of the proposed ILFDs are discussed. The largest measured locking range among four ILFDs is 236.6~245.2 GHz. The highest operation frequency is over 280 GHz. These ILFDs consume 2.97~3.96 mW from a supply of 1.1 V excluding output buffers. Index Terms—Distributed inductor, divide-by-three, injection- locked frequency divider (ILFD), millimeter-wave. I. INTRODUCTION V ARIOUS millimeter-wave applications are attractive such as remote sensing, bio/security imaging, radio astronomy, and high-speed data communications. A mil- limeter-wave phase-locked loop (PLL) is one of the key components in these applications, in which a voltage-con- trolled oscillator (VCO) has the highest frequency. A mil- limeter-wave PLL can be realized by a lower-frequency VCO with a frequency multiplier or a fundamental VCO with a high-frequency divider. In the former, a frequency multiplier may have a limited operation frequency and induces unde- sired spurs and harmonics. The later may have a fundamental VCO with a limited tuning range and a poor phase noise. There is a trade-off between two above approaches to realize a millimeter-wave PLL. In order to relieve the speed require- ments of the following divider chain, a high-frequency divider [1]–[5] is required. Compared with a current-mode divider, an injection-locked frequency divider (ILFD) is one of the good candidates because of its high input sensitivity, low power, and high speed. However, an ILFD may have a limited locking range and is sensitive to process variations. Several CMOS divide-by-2 ILFDs operating above 200 GHz are presented in [3]–[5]. However, the published oper- ation frequency of state-of-the-art CMOS divide-by-3 ILFDs [6]–[12] is much lower than 140 GHz. Generally, the locking range of a conventional divide-by-3 ILFD is narrower than that of a divide-by-2. In this paper, four divide-by-3 ILFDs Manuscript received February 13, 2012; revised July 27, 2012; accepted September 05, 2012. Date of publication November 30, 2012; date of current version January 24, 2013.This paper was approved by Associate Editor Brian Floyd. This work was supported by NTU-MediaTek Lab., and NSC, Taiwan. The authors are with the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan 10617 (e-mail: lsi@cc.ee.ntu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2012.2223932 Fig. 1. The block diagram of a divide-by-3 ILFD. operating above 200 GHz are proposed. A second-harmonic peaking technique is presented to extend the locking range. The distributed inductor technique [13], [14] is also adopted to enhance the operation frequency and the locking range. The paper is organized as follows. Section II reviews the divide-by-3 ILFDs and describes the proposed one with second-harmonic peaking. Section III proposes the divide-by-3 ILFD using distributed inductors and second-harmonic peaking. Section IV gives the experimental results. The conclusions are given in Section V. II. CIRCUIT DESCRIPTION A. Review of Divide-by-3 ILFDs Fig. 1 shows a block diagram of a divide-by-3 ILFD which has a fundamental output frequency of . A frequency doubler generates a second harmonic of . When an input signal with a frequency of mixes with a frequency doubler, the output frequencies of the mixer are expressed as (1) Since an LC-tank has a band-pass characteristic, let us assume that high frequency terms are suppressed and only the funda- mental term is considered. Thus, after mixing and band-pass fil- tering, a divide-by-3 injection-locked output of is achieved. To maintain this injection-locked division, the loop gain of an ILFD should be large enough. The output of the frequency dou- bler (i.e., second harmonic of the ILFD) affects the conversion gain of the mixer and the locking range. While the second har- monic amplitude increases, the locking range can be enhanced. Fig. 2(a) shows a conventional divide-by-3 ILFD [15] where an input signal is applied to an injection NMOS transistor. For Fig. 2(a), the second harmonic is generated by the LC-tank and the injection transistor acts as a mixer. Fig. 2(b) shows another divide-by-3 ILFD using a differential pair as injection transis- tors. For Fig. 2(b), the second harmonic is generated by the non- linearity of the cross-coupled pair which acts as a mixer [6]. For 0018-9200/$31.00 © 2012 IEEE