Two D flip-flops based on bistable-gated- bipolar devices X. Cheng, R. Duane and A. Mathewson Two novel static D flip-flops based on a novel bistable-gated bipolar device are proposed. Their logic functionality and improved speed in comparison to the conventional static D flip-flop are verified with SPICE simulation. Introduction: There are two commonly used CMOS D flip-flops (DFFs) in synchronous digital systems: static and dynamic DFFs. Dynamic DFFs run faster but need refreshing, whereas static DFFs use positive feedback to latch the information, but at slower speed [1]. Negative differential resistance (NDR) devices provide another option to implement static DFFs and improve the speed. One design of NDR- based DFFs has been proposed by Seabaugh et al. [2], using an interband tunnel diode as an NDR device, that can run at a high speed close to dynamic DFFs without regular refreshing. The bistable-gated-bipolar (BGB) device is a novel NDR device that exhibits the NDR characteristic at the body terminal of a metal- oxide-semiconductor (MOS) structure biased in subthreshold. The NDR characteristic is caused by impact ionised carriers generated by the drain current of the MOS structure [3]. Its high peak-to-valley current ratio at room temperature, low standby current, and inherent compatibility with standard CMOS process make it a promising candidate for the ultra-large-scale integration applications. In this Letter, we propose two novel DFFs utilising this NDR device to achieve high-speed and static-storage operation at the same time. Device structure and model: Body contacted SOI technology is preferable to that of bulk silicon owing to significantly reduced body capacitance and area [4]. In contrast to other NDR devices, BGB can be characterised by BSIM3v3 models and readily simulated in SPICE with other transistors [3]. The BSIM3v3 models used here were extracted from Honeywell’s 0.35 mm 3.3 V commercial CMOS SOI technology, where the 400 nm buried oxide layer, specific to SOI devices and therefore absent in the BSIM3v3 models, was modelled externally by an equivalent capacitance of 8.6  10 5 F=m 2 for precise speed evaluation. Fig. 1 Principle of constant-load BGB latch (V s1 ¼ 1.5V, V g1 ¼ 1.86 V, V d1 ¼ 3.3V, V g2 ¼ 0.1 V) ——— I 1 --------- I 2 þ I 3 þ I 4 (DIN ¼ ‘0’) ...... . I 2 þ I 3 þ I 4 (DIN ¼ ‘1’) Latch design: As the basic element in a DFF, two different BGB latches were designed firstly according to the simulated current- voltage storage curve at the storage node (SN). With the same length of 0.35 mm, all NMOSs have a width of 4.4 mm, all PMOSs have a width of 8.8 mm, and BGB devices have a width of 3.2 mm. Each BGB device requires excellent control of its drain, gate and source voltages. Such biasing circuitry is not included in this Letter. The first BGB latch proposed was implemented by directly connect- ing the BGB storage cell [3] to the storage node of a CMOS latch, shown in Fig. 1, termed a constant-load BGB (CLBGB) latch in that the load line is fixed irrespective of the stored state. Its storage curve in Fig. 1 illustrates two stable points at 0.1 and 1.8 V under the optimised bias condition. In addition to meticulous control of the gate voltage (V g2 ) of the load nMOS mld, this scheme requires the load line to be insensitive to the variation of the off-state current (I 3 ) due to the different input data (DIN) for sufficient noise margin. This means the storage currents (I 1 , I 2 ) should be much larger (10) than the variation of the off-state current (0.2 pA=mm). This relationship gives rise to high standby power due to the BGB drain current generating I 1 by impact ionisation at the rate of 6  10 4 . To overcome the above drawbacks, an improved latch circuit is proposed in Fig. 2. The load MOSFET mld in Fig. 1 is split into two (mld1 and mld2) in series, the gates of which are controlled by the clock and the feedback of the output, respectively. When CLK ¼ ‘1’, DIN is driving the storage node with mld1 off to circumvent data conflict. When CLK ¼ ‘0’, the latch is in the retention mode with mld1 on and there are three possible load lines shown in Fig. 2. The choice of load line depends on the storage node voltage precharged by DIN and the present state of DIN. When the storage node has been precharged to low level, mld2 is on and the storage curve follows the on-state load line converging towards ‘0’. When the storage node has been precharged to high level, mld2 is off and the storage curve follows one of the off-state load lines converging towards ‘1’. Although the off-state load current varies with DIN, there is little deviation in the stable ‘1’ voltage due to the exponential I–V relationship when the body-to-source diode begins to turn on [3]. In this way, the retention of ‘0’ and ‘1’ is fulfilled by the on-state and off-state load lines with the stable points at 0 and 1.8V, respectively, and consequently this latch is termed a variable-load BGB (VLBGB) latch. In addition to automatic control of the load gates, this scheme alleviates the constraint of the relationship between BGB current and the off-state current, lowers the BGB current down to the same order of magnitude as the off-state current, and thus decreases its drain current. Fig. 2 Principle of variable-load BGB latch (V s1 ¼ 1.5V, V g1 ¼ 1.82 V, V d1 ¼ 3.3 V) ——— I 1 --------- I 2 þ I 3 þ I 4 (off-state load line when DIN ¼ ‘0’) ...... . I 2 þ I 3 þ I 4 (off-state load line when DIN ¼ ‘1’) -  -  - I 2 þ I 3 þ I 4 (on-state load line) Results and discussions: CLBGB DFF and VLBGB DFF are formed by cascading a pair of master and slave latches proposed above. The DFF function and speed were evaluated by implementing it as a divide-by-two counter. In the function simulations, each counter is running at a low frequency as well as a dummy counter simulated without impaction ionisation models for comparison, shown in Fig. 3. When either stage of latch in a BGB DFF is working in the retention mode, the voltage of its storage node converges towards the corresponding stable point indicated by Figs. 1 and 2 thus realising static storage, while for the dummy, the charge on its storage node tends to leak away with time and ends up with information lost. The DFF standby power mainly comes from the BGB drain currents increasing monotonically with the body voltage. In the speed simulations, the clock frequency is increased until the divide-by-two function begins to fail, which corresponds to the maximum operation frequency. In Table 1, the two novel BGB DFFs are compared against the CMOS static DFF in terms of projected maximum frequency (f max ), dynamic power ( P d ), average standby power ( P s ) and layout area. The speed improvements of the BGB DFFs over a CMOS DFF result from the capacitance reduction along the data path by replacing the feedback branches with BGB storage cells. This also contributes to the significant decrease of both dynamic powers that dominate the total power dissipation in a high-speed system despite their higher standby ELECTRONICS LETTERS 17th March 2005 Vol. 41 No. 6