Energy Efficient Scheduling of Real-Time Tasks on Multicore Processors Euiseong Seo, Jinkyu Jeong, Seonyeong Park, and Joonwon Lee Abstract—Multicore processors deliver a higher throughput at lower power consumption than unicore processors. In the near future, they will thus be widely used in mobile real-time systems. There have been many research on energy-efficient scheduling of real-time tasks using DVS. These approaches must be modified for multicore processors, however, since normally all the cores in a chip must run at the same performance level. Thus, blindly adopting existing DVS algorithms that do not consider the restriction will result in a waste of energy. This article suggests Dynamic Repartitioning algorithm based on existing partitioning approaches of multiprocessor systems. The algorithm dynamically balances the task loads of multiple cores to optimize power consumption during execution. We also suggest Dynamic Core Scaling algorithm, which adjusts the number of active cores to reduce leakage power consumption under low load conditions. Simulation results show that Dynamic Repartitioning can produce energy savings of about 8 percent even with the best energy-efficient partitioning algorithm. The results also show that Dynamic Core Scaling can reduce energy consumption by about 26 percent under low load conditions. Index Terms—Real-time systems, real-time scheduling, low-power design, power-aware systems, multicore processors, multiprocessor systems. Ç 1 INTRODUCTION M OBILE real-time systems have seen rapidly increasing use in sensor networks, satellites, and unmanned vehicles, as well as personal mobile equipment. Thus, the energy efficiency of them is becoming an important issue. The processor is one of the most important power consumers in any computing system. Considering that state-of-the-art real-time systems are evolving in complexity and scale, the demand for high-performance processors will continue to increase. A processor’s performance, however, is directly related to its power consumption. As a result, the processor power consumption is becoming more important issue as their required performance standards increase. Over the last decade, manufacturers competed to advance the performance of processors by raising the clock frequency. However, the dynamic power consumption P dynamic of a CMOS-based processor, the power required during execution of instructions, is related to its clock frequency f and operating voltage V dd as P dynamic / V 2 dd  f . And, the relation V dd / f also holds in these processors. As a result, the dramatically increased power consumption caused by high clock frequency has stopped the race, and they are now concentrating on other ways to improve performance at relatively low clock frequencies. One of the representative results from this effort is multicore architecture [1], which integrates several proces- sing units (known as cores) into a single chip. Multicore processors, which are quickly becoming mainstream, can achieve higher throughput with the same clock frequency. Thus, power consumption in them is a linear function of the throughput. As the demand for concurrent processing and increased energy efficiency grows, it is expected that multicore processors will become widely used in real-time systems. The problem of scheduling real-time tasks on a multicore processor is the same as that of scheduling on a multi- processor system. This is an NP-hard problem [2], and existing heuristic solutions can be divided into two categories. Partitioned scheduling algorithms [3], [4], [5] require every execution of a particular task to take place in the same processor, while global scheduling algorithms [6], [7], [8] permit a given task to be executed upon different processors [6]. Partitioned algorithms are based on a divide- and-conquer strategy. After all tasks have been assigned to their respective cores, the tasks in each core can be scheduled using well-known algorithms such as Earliest Deadline First (EDF) [9] or Rate Monotonic (RM) [10]. Due to their simplicity and efficiency, partitioned scheduling algorithms are generally preferred over global scheduling algorithms. In addition to the innovation of multicore architecture, many up-to-date processors also use dynamic voltage scaling (DVS). DVS adjusts the clock frequency and operating voltage on the fly to meet changes in the performance demand. Multicore processors can also benefit greatly from DVS technology. Because all the cores in a chip are in the same clock domain, however, they must all operate at the same clock frequency and operating voltage [11], [12]. It seems 1540 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 19, NO. 11, NOVEMBER 2008 . E. Seo is with the Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16803. E-mail: euiseong@gmail.com. . J. Jeong, S. Park, and J. Lee are with the Computer Science Division, Korea Advanced Institute of Science and Technology, 373-1 Guseongdong, Yuseonggu, Daejeon 305-701, Korea. E-mail: {jinkyu, parksy}@calab.kaist.ac.kr, joon@kaist.ac.kr. Manuscript received 29 Oct. 2007; accepted 13 June 2008; published online 17 June 2008. Recommended for acceptance by I. Ahmad, K.W. Cameron, and R. Melhem. For information on obtaining reprints of this article, please send e-mail to: tpds@computer.org, and reference IEEECS Log Number TPDS-2007-10-0397. Digital Object Identifier no. 10.1109/TPDS.2008.104. 1045-9219/08/$25.00 ß 2008 IEEE Published by the IEEE Computer Society Authorized licensed use limited to: UNIST. Downloaded on May 26, 2009 at 21:48 from IEEE Xplore. Restrictions apply.