3DIC from Concept to Reality Frank Lee, Bill Shen, Willy Chen, Suk Lee TSMC Design and Technology Platform ABSTRACT 3DIC technology presents a new system integration strategy for the electronics industry to achieve superior system performance with lower power consumption, higher bandwidth, smaller system form factor, and shorter time to -on-Wafer-on- technology opens up a new opportunity to bring 3D chip stacking vision from concept to reality. The provided methodology will be discussed about this market trend and the different pieces needed to jointly make it a success, which includes s blement of multi-die implementation, DFT solution, thermal analysis, verification and new categories of IPs. I. System Integration Future integrated systems will contain billion of transistors, composing tens to hundreds of IP cores. These IP cores are implementing emerging complex multimedia and mobile applications. Efficient data transfers in these IP cores can be achieved through utilization of new methodologies and support design platform. Furthermore, the emerging three-dimensional (3D/2.5D) integration and process technologies allow the design of multi-level Integrated Circuits [1]. In order to satisfy the demands of emerging systems for scaling, performance and functionality, 3D integration is a way to accommodate these requirements in one integrated device. For example, a considerable reduction can be achieved in the number and length of global interconnects using three-dimensional integration and certain IP e.g. wide-IO for memory design. This will gain the benefit of time to market and the size of integrated system. Heterogeneous systems with stacked IC or side-by-side interposer approach can align with many applications such as RF, MEMS, High Voltage, etc. In this work we present an exploration design methodology on the top of interposer with side-by-side structures. Heterogeneous dice of N28HP ARM Cortex-A9 (28nm) N65LP GPS (65nm) N40G DRAM with Wide-IO support (40nm) were integrated together. The floorplan of interposer design is shown in Figure.1 Figure 1. Floorplan of a CoWoS design showing multiple heterogeneous dice During integration stage, there are many issues should be highlighted and need to conquered. Figure 2 is the cross-section view of CoWoS design. Figure 2. Cross-section view of design This design contains thousands of uBumps, TSVs and C4 bumps. In order to fulfill specification requirement, they are around 8.8k uBumps, ~3k TSVs and 1.1k C4 bumps. Bump mapping and assignment need special take care because it requires placement and routing and alignment between die of ubump. TSV/ubump assignment needs work with EDA 978-1-4673-3030-5/13/$31.00 ©2013 IEEE 5A-2 394