A Circuit Compatible Analytical Device Model for Nanowire FET Considering Ballistic and Drift-Diffusion Transport Bipul C Paul ‡† , Ryan Tu ‡ , Shinobu Fujita † , Masaki Okajima † , Thomas Lee ‡ , and Yishio Nishi ‡ ‡ Center for Integrated Systems, Stanford University, Stanford, CA 94305-4070 † Toshiba America Research, 2590 Orchard Parkway, San Jose, CA 95131 ABSTRACT In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and drift-diffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for I-V and C-V characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of a NWFET device. Results show a close match of the model with measured data. 1. INTRODUCTION Continued scaling of transistor sizes into sub-50nm dimensions has made conventional bulk MOSFET devices vulnerable to severe short-channel effects (SCE) such as very high leakage current, poor gate control etc [1, 2]. Various device structures such as double gate fully depleted SOI (DGFDSOI), trigate and all around gate structures hence, are being extensively studied to restrict short-channel effects within a limit while achieving the primary advantages of scaling [2 - 4]. Among these devices nanowire (NW) FETs (a realistic implementation of all-around-gate structure) have recently drawn wide research interest due to their excellent short channel effect immunity compared to other contemporary device structures [5]. The superior I-V characteristics of NWFETs over other devices have been successfully demonstrated both theoretically and experimentally [6-8]. Subsequently, a circuit friendly compact model of these devices will further facilitate the study on their prospect in high performance circuit applications. Though several physical device models are proposed to understand and optimize the characteristics of these devices [6, 9], they are however, not quite efficient for large circuit simulations due to the complexity in solutions, which are mostly numerical. Further, most attempts on nanowire modeling assumed ballistic transport [6, 9] and neglect the more realistic drift-diffusion current conduction. It has been predicted that even in transistors of this kind with channel length below 10nm, expecting ballistic transport is quite unrealistic. A drift-diffusion model of NWFET has recently been reported, where the transistor channel is represented by a number of cascaded ballistic transistors [10]. However, the model requires that all ballistic transistors are operated in the linear region, which is not the case in reality. In this paper, we propose a simplified circuit compatible analytical device model of NWFET for both ballistic and drift-diffusion transport, which can be efficiently used in any conventional circuit simulator like SPICE. The closed form expressions for I-V and C-V characteristics are obtained by analytically solving the device equation with appropriate approximation. We also compare the developed model with measured I-V characteristics of a Ge-NWFET. The rest of the paper is organized as follows. In section 2, the developed compact model of nanowire FET is described considering both ballistic and drift-diffusion current transport. Section 3 presents the experimental verification of the above model with the measured I-V characteristics of a fabricated nanowire PFET followed by a conclusion in Section 4. 2. COMPACT MODEL OF NWFET Conceptually in an NWFET, the nanowire channel is connected between the source and drain contacts, which are in thermodynamic equilibrium. Hence, the electrostatics at source and drain contacts can be described by their individual Fermi level. Since the nanowire channel is isolated from any other source of mobile carrier, source and drain are the sole source of carriers inside the nanowire channel. In such an electrostatic system, the carrier density at any sub-band (nth) of a nanowire channel can be expressed as [9], [ ] dE E f E f E D g n d s E n p n c ) ( ) ( 2 ) ( , μ μ υ υ υ − + − = ∫ ∑ ∞ (1) where μ s(d) is the source (drain) Fermi level, E c,n be the conduction band minimum for the nth sub-band, f(E) is the probability that a state with energy E is occupied. D(E) is the density-of-states and g υ is the valley degeneracy. We assume that the tunneling of carrier from gate to the channel is negligible. Due to unique geometry of NWFET, a relatively large gate insulator thickness can be used while maintaining an excellent gate control and hence, the above assumption is reasonable. Normalizing all energies and voltages by β ( q T k B ) and introducing one-dimensional density of states [9], the total charge in the nanowire channel can be written as ∑ ∫ ∫ ∑ ⎭ ⎬ ⎫ ⎩ ⎨ ⎧ + + + = ∞ − − + − ∞ − + − υ ϕ ε ε ϕ ε ε υ υ υ υ ε ε ε ε 0 )] ( [ 2 / 1 0 ] [ 2 / 1 0 1 1 ds s n s n v n d NW e d e d m g N Q (2) where ) 2 ( 2 0 h π β T k q N B = and m d υ is the density of states effective mass, while n υ ε and φ s ( β ψ s ) are the normalized conduction band minima of n th subband and surface potential, respectively. We consider the source potential as the NSTI-Nanotech 2007, www.nsti.org, ISBN 1420061844 Vol. 3, 2007 691 691