IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 1, NO. 10, OCTOBER 2011 1497 Influence of Bosch Etch Process on Electrical Isolation of TSV Structures Nagarajan Ranganathan,Da Yong Lee, Liu Youhe, Guo-Qiang Lo, Krishnamachar Prasad, and Kin Leong Pey Abstract— Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops. Index Terms— 3-D integrated circuit, bosch etch process, deep reactive ion etching, finite element, leakage current, through silicon vias. I. I NTRODUCTION B ULK silicon micromachining is a ubiquitous technology for diverse applications ranging from MEMS [1], [2], micro-molding [3], wafer level packaging and 3-D integrated circuits and systems [4]–[7]. Though there is a wide range of deep silicon micromachining technologies to choose from, Manuscript received June 5, 2011; revised May 17, 2011; accepted June 13, 2011. Date of publication July 22, 2011; date of current version October 12, 2011. Recommended for publication by Associate Editor K.-N. Chiang upon evaluation of reviewers’ comments. N. Ranganathan, D. Y. Lee, L. Youhe, and G. Q. Lo are with the Institute of Microelectronics, Agency for Science, Technology and Research, 117685, Singapore (e-mail: nathan@ime.a-star.edu.sg; leedy@ime.a-star.edu.sg; liuyh@ime.a-star.edu.sg; logq@ime.a-star.edu.sg). K. Prasad is with the Department of Electrical & Electronic Engineering, Auckland University of Technology, Auckland 1142, New Zealand (e-mail: krishnamachar.prasad@aut.ac.nz). K. L. Pey is with the Division of Microelectronics, School of Electrical & Electronic Engineering, Nanyang Technological University, 639798, Sin- gapore (e-mail: EKLPey@ntu.edu.sg). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2011.2160395 only some can fulfill the diverse requirements for its inte- gration into 3-D microsystems fabrication. Various silicon micromachining technologies have been evaluated for through silicon via (TSV) application, like wet anisotropic etching [8]–[11], laser drilling [12], powder blasting [13], Bosch etch process [14]–[16], cryogenic etching [17]–[20], and reactive ion etching [21]–[23]. However, due to recent developments in inductive coupled plasma etch tools, Bosch etch process has been most preferred due to high etch rates of 5–10 μm/min, better profile control and selectivity to mask of ∼50–100. The Bosch etch process consists of series of isotropic etching and passivation steps caused by rapid switching vbetween etch and passivation process which is normally integral in a reactive ion etch process. The directional ion bombardment from etch step promotes the preferential removal of the passivation film deposited from the previous passivation step on horizontal surfaces, allowing the profile to evolve in a highly anisotropic fashion. Despite its versatility and the exceptionally high etch selectivity to photo resist mask of 50–100:1, a major concern with Bosch process is the sidewall roughness caused by cyclical etch/passivation. It has also been shown that sidewall roughness due to Bosch etch process can significantly affect dielectric and metal step coverage and via-filling [24]. Van Aelst et al. of IMEC, Belgium, have shown that it is possible to reduce or eliminate the undercuts due to Bosch etch process by using a dual mask approach to compensate the undercut [25]. Ming Ji et al. have proposed a parylene deposition process to improve the dielectric uniformity over the rough sidewalls to minimize the leakage current between TSVs [26]. Deniz et al. have proposed a mask-less wet and dry etch processes to smoothen the sidewall to improve the step coverage and reduce leakage between TSVs [27]. However, no detailed studies have been reported on the failure mechanism causing the leakage current. The impact of the sidewall scallops on the thermo-mechanical stress on the TSV dielectric and barrier films has also not been reported. Fig. 1(a)–(d) shows the issues related to Bosch etch process. Fig. 1(e)–(g) are issues related to a typical non-Bosch DRIE process. The motivation of this paper is to focus on the issues associated with sidewall roughness due to deep silicon via etch process. It is therefore the objective of this paper is to study the impact of the scallops on the electrical isolation between adjacent TSV structures. This paper also studies the influence of thermo- mechanical stresses on roughness and smooth sidewall and its influence on the isolation dielectric and barrier layers inside the TSV. 2156–3950/$26.00 © 2011 IEEE