1524 Journal of Power Electronics, Vol. 15, No. 6, pp. 1524-1532, November 2015 http://dx.doi.org/10.6113/JPE.2015.15.6.1524 ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718 JPE 15-6-12 Reduction of Common Mode Voltage in Asymmetrical Dual Inverter Configuration Using Discontinuous Modulating Signal Based PWM Technique M. Harsha Vardhan Reddy † , T. Bramhananda Reddy * , B. Ravindranath Reddy ** , and M. Suryakalavathi ** †,* Dept. of Electrical and Electron. Eng., G. Pulla Reddy Engineering College, Kurnool, Andhra Pradesh, India ** Dept. of Electrical and Electron. Eng., Jawaharlal Nehru Technological University Hyderabad (JNTUH), Hyderabad, Telangana, India Abstract Conventional space vector pulse width modulation based asymmetrical dual inverter configuration produces high common mode voltage (CMV) variations. This CMV causes the flow of common mode current, which adversely affects the motor bearings and electromagnetic interference of nearby electronic systems. In this study, a simple and generalized carrier based pulse width modulation (PWM) technique is proposed for dual inverter configuration. This simple approach generates various continuous and discontinuous modulating signals based PWM algorithms. With the application of the discontinuous modulating signal based PWM algorithm to the asymmetrical dual inverter configuration, the CMV can be reduced with a slightly improved quality of output voltage. The performance of the continuous and discontinuous modulating signals based PWM algorithms is explored through both theoretical and experimental studies. Results show that the discontinuous modulating signal based PWM algorithm efficiently reduces the CMV and switching losses. Key words: Asymmetrical dual inverter configuration, Common mode voltage, Continuous modulating signal, Discontinuous modulating signal, Induction motor, Scalar PWM, Space vector PWM I. INTRODUCTION With the advancement in power semiconductor technology, induction motors receive considerable importance in variable speed drive applications. Three-phase voltage source inverter (VSI) is widely used power electronic converter for induction motor drive applications. Various PWM techniques have been employed to control the output voltage and frequency of VSI [1]-[7]. Among these methods, the continuous PWM (CPWM) (e.g, space vector PWM) and discontinuous PWM (DPWM) techniques display satisfactory performance in terms of DC bus utilization, switching losses, and current ripple [1]-[7]. However, these techniques exhibit high common mode voltage (CMV), which is the potential difference between the neutral point of induction motor and ground. Correspondingly, high switching frequency is employed in VSI to increase its efficiency and reduce its current ripple and filter size. Nonetheless, at high switching frequencies, the sharp edges of CMV cause common mode current, which adversely affects motor bearings [8], [9]. This particular effect can be reduced actively and passively. Passive methods use passive components such as inductors, transformers, and other passive elements [10], [11]. Nevertheless, these passive elements increase the cost, size, and weight of inverter. Active methods involve multilevel inverter topologies [12]-[14] and modified pulse patterns for VSI topologies [15]-[17]. The modified pulse pattern methods for the conventional Manuscript received Feb. 1, 2015; accepted May 20, 2015 Recommended for publication by Associate Editor Dong-Myung Lee. † CorrespondingAuthor:maramreddyharsha@gmail.com Tel: +91-8518270957, G. Pulla Reddy Engineering College * Dept. of Electrical and Electron. Eng., G. Pulla Reddy Engineering College, Kurnool, India ** Dept. of Electrical and Electron. Eng., Jawaharlal Nehru Technological University Hyderabad (JNTUH), India © 2015 KIPE