IEEE TRANSACTIONS ON COMPUTERS, VOL. c-33, NO. 10, OCTOBER 1984 [11] C. D. Thompson, "A complexity theory for VLSI," Ph.D. dissertation, Carnegie-Mellon Univ., Pittsburgh, PA, 1980. [12] S. B. Morris, A. Valiere III, and R. A. Wisniewski, "Processes for random and sequential accessing in dynamic memories," IEEE Trans. Comput., vol. C-28, pp. 225-237, Mar. 1979. [13] J. Lenfant, "Fast random and sequential access to dynamic memories of any size," IEEE Trans. Comput., vol. C-26, pp. 847-855, Sept. 1977. Residue Number System Truth-Table Look-Up Processing -Moduli Selection and Logical Minimization C. C. GUEST, M. M. MIRSALEHI, AND T. K. GAYLORD Abstract -Truth table look-up processing using binary coded residue numbers is investigated for full-precision addition and multiplication for implementations using either electronic or optical technologies. The log- ically minimized numbers of input combinations needed for each opera- tion are presented for moduli 2-23. The moduli sets that require the minimum number of reference patterns are determined for addition and multiplication of 4, 8, 12, and 16 bit words. Index Terms - Content-addressable memory, logical minimization, log- ical reduction, optical processing, programmable array logic, residue number system, truth-table look-up processing. I. INTRODUCTION Recent technological advances and a growing need for parallel application of the same algorithm to large arrays of data have gener- ated renewed interest in the direct implementation of truth-table- based processors. There are three general methods of truth table implementation. 1) Location-addressable memory: The most straightforward implementation of a truth table may be achieved by the storage of the entire truth table in a direct or location-addressable memory (LAM) such as an electronic read-only memory (ROM). These systems require a memory size of S = 2P x q bits where p is the number of input bits and q is the number of output bits. In these processors the inputs determine the address of the answer. 2) Content-addressable memory: The truth table for each output bit may be stored in a content-addressable memory (CAM). A unity result or a null result truth table may be constructed from those' combinations of inputs which cause a particular output bit to be a logical one or a logical zero, respectively. The unity result (null result) truth table represents the canonical sum-of-products (product-of-sums) expression for the logical function corresponding to each output bit. In a content-addressable memory, inputs are compared to the stored tables and detected matches determine the state of each output bit. The stored input words ("reference patterns" in pattern recognition terminology) are the function minterms in the sum-of-products expression or the function maxterms in the product- of-sums expression. The numbers compiled in this correspondence represent the number of function minterms for each output bit for addition and multiplication. In the optical holographic implementation of a content-addressable memory, the number of function minterms represents the number of holograms that need to be stored in the system [1]. Manuscript received May 13, 1983; revised March 20, 1984. This work was supported by the Joint Services Electronics Program and by the National Science Foundation. C. C. Guest is with the Department of Electrical Engineering and Computer Science, University of California at San Diego, La Jolla, CA 92093. M. M. Mirsalehi and T. K. Gaylord are with the School of Electrical Engi- neering, Georgia Institute of Technology, Atlanta, GA 30332. 3) Hardware logic gates: A truth table may also be implemented through the direct use of Boolean logic gates. Each binary output variable when represented as a sum of products (or product of sums) of binary input variables may be implemented with three levels of logic to form a programmable array logic (PAL) device [2]. The numbers compiled in this paper represent the minimum number of AND gates that must be formed to realize each output bit. Independently of how a truth table might be implemented and of which technology might be utilized, it is essential to know how many reference patterns must be recognized in order to judge the size and the complexity of the resulting system. It has recently been shown [1] that the number of reference patterns significantly de- creases if residue arithmetic is used. Also, a laser holographic sys- tem functioning as a content-addressable memory to implement a truth-table look-up processor that operates on binary coded residue numbers has been proposed [1] and its operation analyzed [3]. Such a parallel processor might ultimately be used, for example, to com- pute real-time images from synthetic aperture radar [4]. This type of operation requires several trillion multiplications per second [5],[6]. The results presented here apply both to content- addressable memory systems and to hardware logic gate imple- mentations such as in very large-scale integration (VLSI) design. In VLSI design, the use of PAL's with their highly repetitive geometric structure greatly simplifies the design problem which otherwise may be too time consuming and expensive to attempt [7]. The purpose of this correspondence is to present the minimum sizes of, the truth tables needed to perform full-precision addition and multiplication in the residue number system. The resulting sizes of the truth tables depend on 1) selection of the moduli set, and 2) logical minimization of the corresponding truth tables. The sizes of the reduced truth tables are presented for full-precision addition and multiplication represented as multiple-input single-output operations for moduli 2-23. The moduli sets that are optimum in the sense of requiring the minimum number of reference patterns are determined for the addition and multiplication of pairs of 4, 8, 12, and 16 bit words for both unreduced and reduced truth tables. The number of required reference patterns for each case is deter- mined and compared to the corresponding number for direct binary arithmetic. A related analysis on gating complexity in residue number system computing has been performed by Guffin [8]. However, his results are limited to the special cases of state-change addition and state- change multiplication and further limited to only prime moduli. Papachristou [9] has presented a technique for direct truth table implementation of residue-based functions by an encoding scheme that employs PAL's. In the present research 1) results are presented for each logical expression minimized separately (representing a multiple-input single-output system) even though results for treat- ing sets of logical expressions together (multiple-input multiple- output system) are available during the intermediate steps; and 2) results are presented only for full-precision operations. The very practical and important results for fixed-point and floating-point computations are contained within these more general full-precision results. II. RESIDUE NUMBER SYSTEM TRUTH TABLES The use of residue arithmetic in computing has been extensively studied over many years [10]-[17]. The cyclic nature of residue arithmetic calculations makes this type of arithmetic particularly suitable for implementation by the application of physical properties that are also cyclic in nature. Using the cyclic property of the phase of light, a number of numerical optical residue processors has been developed [1], [3], [18]-[21]. Residue arithmetic has recently been shown to be potentially extremely efficient when applied to CAM- type truth-table look-up processors [1]. In residue arithmetic, the calculations associated with each modulus are independent of the calculations associated with the other moduli; e.g., there are no 0018-9340/84/1000-0927$01.00 © 1984 IEEE 927