International Journal of Computer Applications (0975 – 8887) Volume 19– No.9, April 2011 10 FPGA Implementation of RSA Encryption System Sushanta Kumar Sahu Deptt. of Electronics & Tele-comm. Engg. VSS University of Technology, Burla. Manoranjan Pradhan Deptt. of Electronics & Tele-comm. Engg. VSS University of Technology, Burla. ABSTRACT This paper presents the architecture and modeling of RSA public key encryption/decryption systems. It supports multiple key sizes like 128 bits, 256 bits, 512 bits. Therefore it can easily be fit into the different systems requiring different levels of security. In this paper simple shift and add algorithm is used to implement the blocks. It makes the processing time faster and used comparatively smaller amount of space in the FPGA due to its reusability. Each block is coded with Very High Speed Integrated Circuit Hardware Description Language. The VHDL code is synthesized and simulated using Xilinx-ISE 10.1. It is verified that this architecture support multiple key of 128bits, 256bits, and 512 bits. General Terms Security, Algorithms, Cryptography. Keywords RSA, VHDL, FPGA, modular multiplication. 1. INTRODUCTION The art of keeping messages secure is cryptography. Cryptography plays an important role in the security of data. It enables us to store sensitive information or transmit it across insecure networks so that unauthorized persons cannot read it. The urgency for secure exchange of digital data resulted in large quantities of different encryption algorithms which can be classified into two groups: symmetric key algorithms (with private key algorithms) and asymmetric key algorithms (with public key algorithms) [1]. The asymmetric key algorithm requires two different keys, one for encryption and other for decryption as shown in figure 1. Fig. 1 Public key cryptography The RSA algorithm is a secure, high quality, public key algorithm. It can be used as a method of exchanging secret information such as keys and producing digital signatures. However, the RSA algorithm is very computationally intensive, operating on very large (typically thousands of bits long) integers. A vast numbers and wide varieties of works have been done on this particular field of hardware implementation of RSA encryption algorithm. A hardware implementation of RSA encryption scheme has been proposed by Deng Yuliang & Mao Zhigang. in [2], where they use Montgomery algorithm for modular multiplication. A similar approach has been taken by C. N. Zhang & Y. Xu. in [3]. This design scheme focuses on the implementation of a RSA cryptographic processor using Bit-Serial Systolic Algorithm. This paper describes the implementation of RSA encryption/decryption algorithm on FPGA using 128 bits key size. 2. OVERVIEW OF RSA ALGORITHM Figure 2 summarizes the different steps involved in RSA algorithm. An interesting feature of RSA algorithm is that, it allows most of the components used in encryption process are re-used in the decryption process [5]. So this can minimize the resulting hardware area. Fig. 2 RSA algorithm RSA encryption and decryption are mutual inverses and commutative as shown in equation (1) and (2), due to symmetry in modular arithmetic. Hence the encryption engine covers both the operation of Encryption and Decryption. The mathematics involved in modular arithmetic is as follows: The integers A and B are congruent modulo m if and only if A–B is divisible by m. This congruence is written as: A ≡ B mod m Encryption/ Decryption Plaintext block M is encrypted to a cipher text block C by: C = M e mod n (1) The plaintext block is recovered by: M =C d mod n (2) RSA Key Generation 1. Choose two large primes p and q. 2. Compute n = p q 3. Calculate (n) = (p-1) (q-1) 4. Select the public exponent e € {1, 2, . . . , (n)−1} Such that GCD (e, (n)) = 1. 5. Compute the private key d such that d×e ≡ mod (n) Output: public key: k pub = (n,e) and private key: k pr = (d) Public Key Private Key Plain Text Cipher Text Encryption Decryption Plain Text