Materials Science and Engineering B 154–155 (2008) 95–97 Contents lists available at ScienceDirect Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb Novel enhanced stressors with graded encapsulated SiGe embedded in the source and drain areas Andreas Naumann a,* , Stephan Kronholz b , Anthony Mowry c , Ina Ostermay a , Helmut Bierstedt b , Bernhard Trui b , Kornelia Dittmar b , Peter Kücher a , Johann W. Bartha d , Thorsten Kammler b a Fraunhofer Center Nanoelektronische Technologien, Königsbrücker Landstr.180, 01099 Dresden, Germany b AMD Saxony LLC & Co. KG, Wilschdorfer Landstr.101, 01109 Dresden, Germany c Advanced Micro Devices, 5204 East Ben White Blvd., Austin, TX 78741, USA d IHM, TU Dresden, Nöthnitzer Str. 64, 01187 Dresden, Germany article info Article history: Received 5 May 2008 Received in revised form 20 August 2008 Accepted 3 September 2008 Keywords: SiGe CMOS Stressor Epitaxy Erosion CVD abstract An advanced CMOS scheme for the integration of a graded epitaxial Silicon Germanium (SiGe) layer is presented. SiGe is deposited into the source drain regions right after gate formation to create compressive strain in the transistor channel of the pMOSFETs and thus improve charge carrier mobility. The SiGe layer is exposed to subsequent process steps such as cleaning, implantation and annealing which cause erosion and dopant loss. This effect becomes more severe with increasing Ge content, which is wanted to increase stress in the channel. The negative effect of SiGe erosion on DC transistor performance is shown in this paper and how it can be reduced by optimized SiGe deposition utilizing a two layer stack with different Ge content. First a film with higher Ge concentration is deposited followed by a lower percent Ge film which is aimed to protect the SiGe film underneath. Electrical data for PMOS devices with 55 nm embedded SiGe with 20–30% Ge are presented and compared to the corresponding graded SiGe stack (25–30%, 50 nm with 5 nm thick 15% cap). Comparing Embedded Silicon Germanium (eSiGe) devices with 30 at% Ge, we see a 5% I DSAT improvement for the graded layer over the monolithic one. © 2008 Elsevier B.V. All rights reserved. 1. Introduction By introducing mechanical strain during wafer processing it is possible to engineer the channel mobility of CMOS transistors. Embedded Silicon Germanium (eSiGe) in the source and drain regions (S/D) of pMOSFETs causes uniaxial compressive strain in the channel region which increases the hole mobility and thus the transistor performance. This strain can be enhanced either by moving the SiGe in the S/D closer to the transistor channel [1] or by increasing the lattice mis- match between Si and SiGe with using higher Ge concentrations. In this work we evaluate the latter by modifying the deposition processes of the eSiGe. 2. Device fabrication For the fabrication of MOS transistors, the 65 nm CMOS on SOI Technology of AMD was used [2]. The integration of eSiGe was already described in refs. [3,4]. * Corresponding author. Tel.: +49 351 277 4540; fax: +49 351 2779 4540. E-mail address: andreas.naumann@amd.com (A. Naumann). For this work only the SiGe deposition process was changed while all other process steps of the CMOS fabrication remained unchanged. A standard wet cleaning procedure was used (SC1, SC2, diluted HF), followed by a plasma in-situ cleaning procedure inside the deposition tool before the epitaxy was started in a UHV-CVD chamber. Monolithic SiGe layers from 22 at% Ge to 30 at% were manufac- tured. Some of the wafers got a stack consisting of 5 nm 15 at% Ge layer on top of a 25–30at% base layer. The Germanium concentra- tion in the two layers of the stack was constant and the change between the two layers was abrupt. The total SiGe thickness was kept constant at 55 nm. The composition of the SiGe was measured by HRXRD, the thickness by optical ellipsometry and the thickness of the thin top layer was controlled by TEM imaging. With HRXRD (on large areas) it was confirmed that all layers are fully strained and no crystal defects were observed by TEM imaging Fig. 1. 3. Results and discussion The p-active sheet resistance and the drain current (I D,Sat ) of the pMOS transistors were measured for the transistors fabricated with the different SiGe processes. The overlap capacitance and the threshold voltage were comparable for all devices. 0921-5107/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2008.09.024