Threshold Voltage Drift and On-Resistance of SiC Symmetrical and Asymmetrical Double-trench MOSFETs Under Gate Bias Stress Juefei Yang 1 , Saeed Jahdi 1 , Bernard Stark 1 , Phil Mellor 1 , Ruizhu Wu 2 , Jose Ortiz-Gonzalez 2 , Olayiwola Alatise 2 1 University of Bristol, United Kingdom 2 University of Warwick, United Kingdom Corresponding author: Juefei Yang, juefei.yang@bristol.ac.uk Abstract In this paper, long-period positive and negative DC gate bias stressing is applied on the SiC symmetrical and asymmetrical double-trench MOSFETs for a wide range of temperatures in comparison with SiC planar MOSFETs. The magnitude of gate stress are within the recommended ranges by manufacturers with clear threshold voltage drift being observed. Also, the post-stress drift of on-state resistance at both high and low applied gate-source voltages is measured. The impact of temperature on these parameters are shown to vary for different structured MOSFETs. 1 Introduction Power electronics is the technology enabler of grid- connection of renewables [1] by use of SiC power MOSFETs. Gate defects of SiC MOSFETs are source of major reliability concerns. SiC MOS- FET is more sensitive to gate stressing than Sil- icon MOSFETs. As a consequence of electron and hole capturing by traps on the gate oxide under the impact of applied gate voltage, threshold voltage drift is induced. Unlike Silicon MOSFET, SiC MOS- FET is more sensitive to gate stressing because there is Carbon present at the oxide-channel inter- face contributing to presence of traps, as well as its wide-bandgap properties which makes the traps of higher energy level involved in the trapping/de- trapping of carriers [2]. The threshold voltage drift directly affects the operation by increasing the con- duction losses when threshold drifts up and will in- crease the likelihood of parasitic turn-ON [3] when threshold drifts down. The introduction of double- trench structured SiC MOSFETs as a competitor to conventional planar MOSFETs changes these facts as its double-trench structure allows high channel- density design thus enables lower on-state loss and faster switching with different parasitic elements. The three cross-sectional schematics for planar structure, symmetrical and asymmetrical double- trench MOSFETs are shown in Fig. 1. In this paper, the threshold voltage instability under DC gate bias- ing are investigated and compared for these three devices at a range of temperature. Fig. 1: From top: cross-section of SiC Planar MOS- FET, Symmetrical Double-Trench SiC MOSFET & Asymmetrical Double-trench SiC MOSFET.