Fault-Tolerance and Noise Modelling in Nanoscale Circuit Design Jahanzeb Anwer, Ahmad Fayyaz, Muhammad M. Masud and Saleem F. Shaukat Electrical Engineering Department COMSATS Institute of Information Technology Defense Road, Off-Raiwand Road, Lahore, Pakistan Contact No: +60136057683 jahanzebanwer2002@gmail.com Usman Khalid and Nor H. Hamid Electrical & Electronics Engineering Department Universiti Teknologi PETRONAS Bandar Seri Iskandar, Tronoh, Perak, Malaysia Contact No: +60192786127 hishmid@petronas.com.my Abstract— Fault-tolerance in integrated circuit design has become an alarming issue for circuit designers and semiconductor industries wishing to downscale transistor dimensions to their utmost. The motivation to conduct research on fault-tolerant design is backed by the observation that the noise which was ineffective in the large-dimension circuits is expected to cause a significant downgraded performance in low- scaled transistor operation of future CMOS technology models. This paper is destined to give an overview of all the major fault- tolerance techniques and noise models proposed so far. Summing and analysing all this work, we have divided the literature into three categories and discussed their applicability in terms of proposing circuit design modifications, finding output error probability or methods proposed to achieve highly accurate simulation results. INTRODUCTION The key area of research in integrated circuit design attracting many engineers and scientists is fault-tolerant computation. The need for this research arose from the need to downscale transistor dimensions for our future digital circuits (to achieve high device density). During the downscaling period, signal level has been decreasing at a fast pace whereas amount of noise is the same causing a high signal error-rate for upcoming transistor models. Therefore, we are in dire need to model noise in nanoscale circuits for simulation purposes. The research of fault-tolerant design can be divided into three categories (based on the literature available). The first approach works on the transistor level i.e. proposing modifications in the circuit design (based on mathematical models) that can cater noise present in the circuit. The second approach is to design error-probabilistic schemes that can let the designer know how fault-tolerant his circuit is, by providing the output error probability of his circuit. The final approach proposes realistic simulation models that can take into account effect of noise dominant in nanoscale design only. The information regarding the extent to which certain transistor parameters affect the noise immunity of a circuit also comes in the third category. The common design strategy to be noticed in all these models (except for redundancy) is their dependence on probabilistic computation [1], [2]. Probabilistic analysis is used because the nature of noise is random (or probabilistic). Now, we are going to discuss the fault-tolerant design schemes and their scope followed by a general discussion on their applicability and effectiveness. A. Redundancy Redundancy is the basic approach to design a fault-tolerant circuit model [1]. The idea of this technique is to introduce redundancy for each gate in the circuit (or for that portion of the circuit probable of being in error) and then taking the output from the majority output decision of the original and copied gates so that if one gate in the redundant combination is faulty, the output is not affected. This technique is further divided into triple modular redundancy (TMR), cascaded triple modular redundancy (CTMR) and triple interwoven redundancy (TIR). B. Markov Random Field(MRF) model The most significant noise at the nanoscale level is the thermal noise. To deal with this noise, MRF equivalents [3] of universal gates have been proposed that can very well isolate the effect of thermal noise in the circuit and prevent it from affecting the final output. The final output comes out to be clean as if there were no noise in the circuit. According to this model, a Gaussian noise source is added at the input of each logic gate. This noise source is accounted for the thermal noise generated from all the components in the previous circuit stage. In this way, the thermal noise effect of the previous stage is catered by the MRF equivalent of the current stage unless we are left with thermal noise affect of final stage of the circuit only. A more analytical model of thermal noise is rather impractical (that can model thermal noise originating from every component of a circuit); we consider the thermal noise model in this technique to be adequate for simulation purposes. We generated random noise data in MATLAB and integrated it with the VPWLF function in Cadence Analog Design Environment. By adding the VPWLF noise source at the input of every circuit stage (in the transistor-level schematic), we can model the effects of thermal noise. This noise, if added to a digital pulse input would look like as shown in Fig 1. Simulations ([3] and [4]) show that modeling thermal noise in a circuit cause many unnecessary bit reversals in simple CMOS gate as compared to almost noiseless output of MRF-CMOS gate. The drawback of this technique is the immense increase in the number of transistors required for a simple circuit. But, for improved circuit reliability, high transistor count is the price a circuit designer has to pay. (Interested readers can find MRF mathematical model in [5] and MRF-CMOS transformation method in [4]).