IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRUARY 2001 227 Reconfigurable VLSI Architectures for Evolvable Hardware: From Experimental Field Programmable Transistor Arrays to Evolution-Oriented Chips Adrian Stoica, Ricardo Zebulum, Didier Keymeulen, Raoul Tawel, Taher Daud, and Anil Thakoor Abstract—Evolvable hardware (EHW) addresses on-chip adapta- tion and self-configuration through evolutionary algorithms. Current programmable devices, in particular the analog ones, lack evolution-ori- ented characteristics. This paper proposes an evolution-oriented field programmable transistor array (FPTA), reconfigurable at transistor level. The FPTA allows evolutionary experiments with reconfiguration at various levels of granularity. Experiments in SPICE simulations and directly on a reconfigurable FPTA chip demonstrate how the evolutionary approach can be used to automatically synthesize a variety of analog and digital circuits. Index Terms—Adaptive computing, evolvable hardware, field-pro- grammable transistor arrays (FPTAs), genetic algorithms, reconfigurable VLSI architectures. I. INTRODUCTION The idea behind evolutionary circuit synthesis/design and evolvable hardware (EHW) is to employ a genetic search/optimization algorithm that operates in the space of all possible circuits and determines solution circuits that satisfy imposed specifications, including target functional response, size, speed, power, etc. Currently, the search for a circuit solution can be performed using software simulations [1] or directly in hardware on reconfigurable chips [2], [17]. However, software simulations take too long for prac- tical purposes, since the simulation time for one circuit is multiplied by the large number of evaluations required by evolutionary algorithms. In addition the resulting circuit may not be easily implemented in hardware, unless implementation constraints are imposed during evolution. Hardware evaluations can reduce by orders of magnitude the time to get the response of a candidate circuit, potentially reducing the evolution time from days to seconds [3]. Hardware evaluations commonly use commercial reconfigurable devices, such as field programmable gate arrays (FPGAs) [4] or field programmable analog arrays (FPAAs) [3]. These devices, designed for several applications other than EHW, lack evolution-oriented features, and, in particular the analog ones, are suboptimal for EHW applications. This paper addresses devices specifically targeted for EHW, in par- ticular those allowing analog processing. It proposes an architecture on which both analog and digital circuits can be synthesized by evo- lutionary means. The paper is organized as follows. Section II pro- vides background on circuit synthesis using evolutionary algorithms. Section III reviews efforts toward evolution-oriented reconfigurable ar- chitectures (EORA), focusing on programmable analog devices. Sec- tion IV introduces the FPTA and Section V illustrates evolutionary ex- periments performed on this device. Following these, portability, mix- trinsic evolution issues are discussed in Section VI followed by con- clusions in Section VII. Manuscript received February 17, 2000; revised July 18, 2000. This work was performed at the Center for Integrated Space Microsystems, Jet Propulsion Laboratory, California Institute of Technology. This work was supported by the Defense Advanced Research Projects Agency and by the National Aeronautics and Space Administration. The authors are with the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA 91109 USA (e-mail: adrian.stoica@jpl.nasa.gov). Publisher Item Identifier S 1063-8210(01)00802-2. II. BACKGROUND The genetic search in EHW is tightly coupled with a coded represen- tation that associates each circuit to a “genetic code” or chromosome. The simplest representation of a chromosome is a binary string, a suc- cession of 0s and 1s that encodes a circuit. The main steps of evolu- tionary synthesis are illustrated in Fig. 1. First, a population of chromosomes is randomly generated. The chro- mosomes are converted into circuit models for evaluation in SW, in which case the evolution is called extrinsic, or into control bitstrings downloaded to programmable hardware. The latter is referred to as intrinsic EHW. Circuit responses are compared against specifications, and individuals are ranked based on how close they come to satisfying them. In preparation for a new iteration, a new population of individuals is generated from the pool of best individuals in the previous genera- tion. This is subject to a probabilistic selection of individuals from a best individuals pool, followed by two operations: random swapping of parts of their chromosomes, the crossover operation, and random flipping of chromosome bits, the mutation operation. The process is repeated for several generations, resulting in increasingly better indi- viduals [1]. Randomness helps to avoid getting trapped in local optima. Monotonic convergence (in a loose Pareto sense) can be forced by unal- tered transference to the next generation of the best individual from the previous generation. There is no theoretical guarantee that the global optimum will be reached in a useful amount of time; however, the evo- lutionary/genetic search is considered by many to be the best choice for very large, highly unknown search spaces. The search process is usually stopped after a number of generations or when closeness to the target response has reached a sufficient degree. One or several solutions may be found among the individuals of the last generation. Evolution can either be online or offline. Evolution is online when the circuit actively changes the behavior of a functional system such as a robot operating in a target environment. III. RECONFIGURABLE ARCHITECTURES FOR EHW EXPERIMENTS A. Toward Evolution-Oriented Reconfigurable Architectures This discussion is mainly in the context of devices supporting evo- lution of analog circuits. To best support EHW one must consider sev- eral aspects for EORA. The granularity of the programmable chip is an important feature. A first limitation of FPAAs is their coarse gran- ularity, basically the operational amplifier level. For FPGAs the finest granularity is at the gate level, which may be sufficient for evolution of digital circuits. However, using FPGAs to evolve analog circuits, as shown possible in [2], is not an efficient technique for obtaining analog functionality. From the EHW perspective, it is interesting to have programmable granularity, allowing the sampling of novel architectures together with the possibility of implementing standard ones. The optimal choice of elementary block-type and granularity is task dependent. At least for experimental work in EHW, it appears a good choice to build reconfig- urable hardware based on elements of the lowest level of granularity. Virtual higher level building blocks can be considered by imposing pro- gramming constraints. An example would entail forcing groups of el- ementary cells to act as a whole, e.g., by freezing certain parts of their configuration bitstrings that describe say a NAND gate. Ideally, the “vir- tual blocks” for evolution should be automatically defined/clustered during evolution [1]. EORA should be transparent architectures, allowing the analysis and simulation of the evolved circuits. They should also be robust enough not to be damaged by any bitstring configuration existent in the search space, potentially sampled by evolution. Finally, EORA should allow evolution of both analog and digital functions. 1063–8210/01$10.00 © 2001 IEEE