2724 IEEE TRANSACTIONS ON MAGNETICS, VOL. 42, NO. 10, OCTOBER 2006 1.8 V Power Supply 16 Mb-MRAMs With 42.3% Array Efficiency Hiroaki Yoda , Tadashi Kai , Tsuneo Inaba , Yoshihisa Iwata , Naoharu Shimomura , Sumio Ikegawa , Kenji Tsuchida , Yoshiaki Asao ,Tatsuya Kishi , Tomomasa Ueda , Shigeki Takahashi , Makoto Nagamine , Takeshi Kajiyama , Masatoshi Yoshikawa , Minoru Amano , Toshihiko Nagase , Keiji Hosotani , Masahiko Nakayama , Yuui Shimizu , Hisanori Aikawa , Katsuya Nishiyama , Eiji Kitagawa , Ryousuke Takizawa , Yoshihiro Ueda , Masayoshi Iwayama , and Kiyotaro Itagaki SoC Research and Development center, Toshiba Corporation, Yokohama 235-8522, Japan Corporate Research & Development Center, Toshiba Corporation, Kawasaki 212-8582, Japan Toshiba Corp., Semiconductor Company, Yokohama 247-8585, Japan Technologies for realizing high density MRAM were developed. First, new circuitry to lower the resistance of programming wires was developed. Second, both MTJ plane shape and cross-sectional structure were optimized to lower the programming current. Based on these two technologies, 16 Mb MRAM was designed, fabricated with 130 nm CMOS process and 240 nm back end MTJ process. As a result, a 1.8 V power supply MRAM with 42.3% array efficiency was successfully demonstrated. Index Terms—Magnetic tunnel junction (MTJ), magnetoresistive random access memory (MRAM). I. INTRODUCTION M RAM is the most promising candidate for a nonvolatile random access memory because of its unlimited en- durance which other nonvolatile memories lack. Excellent work has proved the validity of MRAM [1]. Next, competitiveness against existing memories should be added. Low voltage oper- ation and reasonable array efficiency are items to be achieved especially for stand alone application. In this paper, technolo- gies for low voltage operation and reasonable array efficiency were developed, implemented, and successfully demonstrated. II. STRATEGY FOR LOWERING OPERATION VOLTAGE AND INCREASING ARRAY EFFICIENCY Every four programming wires were connected in the middle of the subarrays as shown in Fig. 1. In programming one of the left half cells, one of the left transistor and all of the four right transistors are turned on. Then, the programming current flows in one wire at the left half and into four wires at the middle. The effective wire resistance was reduced to 62.5% of the conventional case. As a result, reasonably large 512 rows 512 columns subarray was able to be adopted which led to the highest array efficiency of 42.3% among those ever reported. For high speed operation of 100 MHz in burst mode, a rise time of the programming current must be shorter than 10 ns. A new driving sequence was adopted as shown in Fig. 2. First, the left EN SRC transistor is turned on while the right EN SINK transistor off, and then the current flows to charge the parasitic capacitance. Second, before the current starts decreasing, the EN SINK transistor is turned on, and then the current is in- creased to reach the preset programming value. This proposed sequence realized 7.5 ns. rise-time which is faster than a con- ventional as simulated in Fig. 3. Digital Object Identifier 10.1109/TMAG.2006.880081 Fig. 1. New circuitry. Fig. 2. Driving sequence of the programming current. (Color version available online at http://ieeexplore.ieee.org.) III. CIRCUITRY DESIGN Supply voltage is mainly consumed in switch transistors and programming wires in writing data. Reducing both those resis- tances and programming current is a must for the low voltage operation. Dividing 16 Mb into small subarrays is one of the ways to reduce the wire resistance. However, this leads to in- creasing peripheral area, i.e., to low array efficiency. Therefore, in this study, new circuitry was developed to lower the wire 0018-9464/$20.00 © 2006 IEEE