2008 IEEE 2008 IEEE Symposium on VLSI Circuits A Process-Scalable Low-Power Charge-Domain 13-bit Pipeline ADC Michael Anthony, Edward Kohler, Jeffrey Kurtze, Lawrence Kushner, Gerhard Sollner Kenet, Inc., Woburn MA, USA www.kenetinc.com Abstract A 13-bit ADC is implemented using a novel charge-domain architecture. Enhanced bucket-brigade circuitry and a tapered charge pipeline provide precision charge-domain operation in a standard CMOS process, while eliminating the need for signal-path op-amps. The prototype ADC, implemented in 0.18μm CMOS, provides 10.65 ENOB at 250 MS/s while consuming only 140 mW, yielding an exceptionally low FoM of 0.28 pJ/conversion-step. Simulations indicate that the architecture and circuitry are well suited to scaling below 90nm. Introduction Pipeline ADCs are widely used in applications that require both high sample rate and high resolution. Most such ADCs employ switched-capacitor circuitry, using op-amps for pipelining and inter-stage gain. This architecture has proved challenging to scale to sub-100 nm processes, especially when maintaining or reducing power consumption is important. Some recent work has sought alternatives to op-amps in pipeline ADCs, such as the use of open-loop amplifiers with digital correction[1] and comparator-based switched-capacitor circuits[2]. CCD-based charge-domain pipelines offer another alternative[3], but their performance is limited when fabricated in standard CMOS processes. Bucket-brigade devices (BBDs) provide charge pipelining and are fully compatible with standard CMOS processes, but conventional BBDs have severely limited speed and accuracy[4]. This paper describes a charge-domain pipeline ADC using enhanced BBD circuitry which provides significantly improved speed and accuracy at very low power. BBD with boosted charge transfer Charge transfer in a conventional BBD is depicted in the upper circuit and waveforms of Fig. 1. The gate of charge-transfer FET M 1 is held at a constant voltage V G . Its drain, the output node OUT, is held at a high voltage. The charge to be transferred is stored on capacitor C, resulting in an initial voltage at M 1 ’s source which is dependent on that charge. M 1 is initially off. The charge-transfer clock voltage V T is initially high. Charge transfer is initiated by a negative V T step which is coupled to the source of M 1 via C. M 1 turns on, conveying (negative) charge from C to OUT. After the initial negative excursion caused by the V T step, V S rises towards a cutoff value approximately equal to V G -V t . Charge transfer ends when V T returns to its original value. The charge transferred from C to OUT is equal to the initial charge present on C plus a constant offset, plus an error term due to incomplete settling of V S . This error term is dependent on the charge being transferred. Its linear component results in charge-transfer gain less than 1; its nonlinear component causes charge-transfer nonlinearity. These charge-transfer errors in conventional BBDs are too large to support use in high-performance pipeline ADCs. Fig. 1 Conventional and boosted BBD charge transfer BBD charge-transfer accuracy and speed are improved by the addition of a ‘booster’ amplifier A as shown in the lower circuit of Fig. 1. The resulting waveforms are similar to those just described, except that M 1 ’s gate voltage is no longer constant: amplifier A drives the gate of M 1 such that V S settles towards reference voltage V 0 . The amplifier gain reduces both the settling time and the final error voltage at V S . For high sample rate, amplifier A must have high slewing speed and bandwidth. Relatively low gain (20-50) is sufficient for high-precision ADC applications. Fig. 2 shows a practical implementation of a boosted charge-transfer circuit. Fig. 2 Practical boosted charge-transfer stage and operating equations The amplifier in Fig. 2 consists of common-source FET M 2 , cascode FET M 3 , and current-source load MP 1 . Effective V 0 is the gate voltage of M 2 at which I D of M 2 balances I D of MP 1 . This circuit provides gain of roughly 50 and GBW of 10GHz in the 0.18μm process used for the reported ADC. Circuit simulations indicate that similar gain and higher speed can be obtained in a 65nm process, with reduced power consumption.