IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 1, JANUARY 2014 95 An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at 0 V Achieving Zero Leakage With 400-ns Wakeup Time for ULP Applications Sudhanshu Khanna, Member, IEEE, Steven C. Bartling, Michael Clinton, Member, IEEE, Scott Summerfelt, John A. Rodriguez, Member, IEEE, and Hugh P. McAdams Abstract—This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to re- store the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher per- formance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply. Index Terms—Ferroelectric RAM (FRAM), low power, micro- controllers, nonvolatile logic (NVL). I. INTRODUCTION A DVANCES in low-power VLSI design over the last two decades have made ICs pervasive in our lives. We are surrounded by smart systems like ambient sensors, home automation, and implantable/wearable fitness and medical devices. These embedded systems have varied applications and system requirements. They also have lower volumes and system cost than consumer products like laptops or cell phones. Hence, programmable solutions like low-power 16–32-b micro- controllers (MCUs) are preferred over ASICs or subthreshold systems which have a limited use or performance range. Manuscript received April 28, 2013; revised August 14, 2013; accepted September 02, 2013. Date of publication October 18, 2013; date of current version December 20, 2013. This paper was approved by Guest Editor Byeong-Gyu Nam. S. Khanna, S. C. Bartling, S. Summerfelt, J. A. Rodriguez, and H. P. McAdams are with Texas Instruments, Dallas, TX 75243 USA (e-mail: skhanna@ti.com). M. Clinton was with Texas Instruments, Dallas, TX 75243 USA. He is now with TSMC, Austin, TX 78759 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2013.2284367 Lowering power consumption is the key design challenge in this application space. To reduce dynamic power techniques like clock gating, dynamic voltage scaling, low-voltage operation, efficient RTL design, and optimized standard cell libraries are employed [1], [2]. However, since these applications sleep for a majority of their lifetime, reducing standby power is even more critical. For this reason, state-of-the-art ultralow-power (ULP) SoCs are developed using older technology nodes like 90 nm or 130 nm. In ULP MCU SoCs, standby power is dominated by digital logic and memory leakage and the on-chip power-man- agement quiescent current. To achieve the standby power goals, SoCs implement complex power management schemes. Mul- tiple sleep modes with varying degrees of power gating are used. This eliminates leakage from the digital sections of the SoC and allows the associated LDOs to be turned off as well. How- ever, power gating causes flip-flops to lose their saved state. This means that, every time the SoC comes back from sleep, the MCU has to boot up again. The boot-up process takes thou- sands of cycles, hundreds of microseconds, and hundreds of nanojoules of energy. The boot-up process is costly for pro- grammable SoCs because these SoCs are built for a range of applications and cost points and are configured at boot. Trim and calibration for power management and analog is also done at boot. This factory boot is then followed by the customers boot-up code. For simple applications like a temperature sensor, boot-up becomes the major component of the overall energy and time cost. Applications that need lower latencies would not be feasible at all due to boot-up time. To prevent having to boot-up after sleep mode, a technique called retention is used where the slave stage of each flip-flop is on a separate “always-on” supply which is not power-gated. This helps decrease wakeup time and energy by eliminating need for boot-up but it increases the standby power due to the “always-on” retention flip-flops and the LDO generating the “always-on” supply. In this manner, dif- ferent sleep modes trade off sleep mode leakage, wakeup time, and design volatility. We present an MCU SoC that achieves zero sleep mode leakage while still having an ultrafast 400-ns wakeup time. We achieve 100% digital state retention. No boot-up is required after a power cycle. Before going into sleep mode, data from all flip-flops and latches in the system are transferred to custom fer- roelectric-capacitor (FeCap)-based nonvolatile memory arrays called NVL arrays. The SoC has traditional ferroelectric RAM 0018-9200 © 2013 IEEE