This paper describes an optimization toolbased design strategy for a Current Mode Logic CML divideby2 circuit. Representing a building block for output frequency generation in a RFID protocol basedfrequency synthesizer, the circuit was designed to minimize the power consumption for driving of multiple loads with unbalancing (at transceiver level). Implemented with XFAB XC08 180 nm technology, the circuit was optimized through MunEDA WiCkeD tool at Cadence Virtuoso Analog Design Environment ADE. Divideby2 circuit, CMOS technology, PLL phase lockedloop, optimization tool, CML current mode logic, RF transceiver. I. INTRODUCTION N the last decades, radio frequency waves have attracted the interest from academia and industry due to a number of attractive features of radio frequency wavebased devices to provide gigabit level transmission rate through wireless communication systems. In this context, phaselocked loop PLLbased frequency synthesizers play a critical role [1] for stable reference frequency generation with precise channel spacing and acceptable level of phase noise. Widely utilized in communication systems for transceiver implementation operating at radio frequency RF range, PLL based circuits perform a precise output frequency generation by establishing a stable correlation (in phase and frequency) between output and input frequencies by phase comparison. Working through large signal operation, frequency dividers are the building blocks responsible for interfacing different frequency levels with the required precision. In this particular application context, divideby2 circuits generate the set of PLL outputs for the connection and driving of the loads at transmitter and receiver level to ensure the system operation with the required reference frequency and with acceptable levels of harmonic degradation. This paper aims to describe the structure, operating features Agord de Matos Pinto Jr. is analog radio frequency RF designer at CT2 Training Center 2 from IC Brazil Program, SP, Brazil (phone: +55 19 3746 6154, email: agordjr@ct2.cibrasil.gov.br). Yuzo Iano works as an associate Professor in electrical and computer engineering in Communications Department at School of Electrical and Computer Engineering at University of Campinas  Unicamp, SP, Brazil (phone: +55 1935213809, email: yuzo@decom.fee.unicamp.br). Leandro Tiago Manera is a Professor in electrical and computer engineering in Semiconductors, Instruments and Photonics Department of School of Electrical and Computer Engineering  Unicamp, SP, Brazil (phone: +55 19 35213727, email: manera@dsif.fee.unicamp.br). Raphael Ronald Noal Souza is analog RF designer and project coordinator at CT2 from IC Brazil Program and Ph.D. student at Unicamp, SP, Brazil (phone: +55 19 37466154, email: raphael.souza@ct2.cibrasil.gov.br). and design strategy applied for the implementation of a divide by2 circuit, PLL building block for System on Chip SoC design in a RFID protocol basedtransceiver. PLL structure is composed by a phasefrequency detector (PFD), a charge pump (CP), a lowpass filter (LPF), a voltage controlled oscillator (VCO), and a divideby2 circuit (DIV2) in the feed forward path, and a programmable loop divider in the feedback path, according to the block diagram on Fig. 1. Defined for high frequency applications, the system comprises a set of technical features specified from ISO/IEC 180004, by applying a frequency range based on the unlicensed Industrial, Scientific and Medical ISM band (used in item management applications) centered at 2.4375 GHz. In this case, the general set of PLL operating features includes 16 communication channels, 5 MHzbased channel spacing and frequency range from 2.4 GHz to 2.475 GHz. Design process was performed at Cadence Virtuoso Analog Design Environment ADE and optimized at MunEDA WiCkeD by applying XFAB XC08 180 nm CMOS technology. Thus, Section II presents the project description, Section III describes the design procedures for divideby2 circuit, Section IV presents the obtained results, and finally Section V proposes the final conclusions. II.PROJECT DESCRIPTION    Designed as a RFID protocolbased RF transceiver, the system architecture is composed by 3 operating modules, as illustrated from the block diagram (with the corresponding pattern of connections), on Fig 2. According to the block diagram, divideby2 circuit DIV2 is highlighted in gray and the building blocks to be driven are highlighted in white. Homodyne receiver (on the bottom of the diagram) demands two balanced pairs of differential signals for driving the pair of downconversion mixers (in different architecture branches): one pair in phase for I branch (LO_I and LO_In), and one pair in quadrature for Q branch (LO_Q and LO_Qn). With a singleended structure, transmitter (on the top of the diagram) demands only one connection from DIV2 (LO_I) for driving the modulator (for upconversion operation). Third order type II PLLbased frequency synthesizer (on the middle of the diagram) requires one pair of differential signals (LO_Q and LO_Qn) from DIV2 for driving the programmable loop divider on feedback path. An Optimization ToolBased Design Strategy Applied to Divideby2 Circuits with Unbalanced Loads Agord M. Pinto Jr., Yuzo Iano, Leandro T. Manera, Raphael R. N. Souza I World Academy of Science, Engineering and Technology International Journal of Electrical and Computer Engineering Vol:9, No:6, 2015 526 International Scholarly and Scientific Research & Innovation 9(6) 2015 ISNI:0000000091950263 Open Science Index, Electrical and Computer Engineering Vol:9, No:6, 2015 publications.waset.org/10001612/pdf