Research Article New Proposal for MCML Based Three-Input Logic Implementation Neeta Pandey, 1 Kirti Gupta, 2 and Bharat Choudhary 1 1 Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India 2 Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, Delhi, India Correspondence should be addressed to Neeta Pandey; n66pandey@redifmail.com Received 31 December 2015; Revised 8 June 2016; Accepted 19 July 2016 Academic Editor: Spyros Tragoudas Copyright © 2016 Neeta Pandey et al. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Tis paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. Te conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. Te new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. Te performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. Te sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included. 1. Introduction MCML style fnds application in communication systems, optical fber links, digital to analog converter, micropro- cessors, and signal processors [1–3]. As compared to static CMOS logic, MCML has several advantageous features such as improved signal integrity, reduced power consumption, better power delay product at high frequencies, stability with technology generations, and improved security in cryptog- raphy applications [4–9]. A MCML gate consists of three main parts, namely, a pull down network (PDN), a current source, and a load. Te PDN implements the logic function; the current source generates the constant bias current while the load performs the current-to-voltage conversion. Te logic function is realized using series-gating approach which suggests stacking of the source-coupled transistors pairs in the PDN. Te number of stacked levels has a direct correspondence with number of inputs in the logic function. As the number of inputs becomes larger, there is increase in the number of stacked levels (NSL). For proper operation of MCML gate, a minimum power supply is required which is decided by the value of NSL and higher NSL result in larger minimum power supply. Tis serves as a main motivation behind using low voltage topology as lower power supply will result in reduced power consumption since the latter is computed as the product of bias current and power supply. Few low voltage techniques are available in the open literature [10–16]. Te techniques [10–13] provide single ended output. A NOR based logic realization is proposed in [10, 11] to avoid stacking but it requires multistage realization of logic function. Additional current mirror, voltage, and current source are employed in [12, 13] to avoid stacking. Te triple-tail cell concept is introduced in [14–16] to reduce NSL by one for the two-level MCML gates implementation. Tis paper introduces a new methodology for reducing the value of NSL by two and presents a quad-tail cell for this purpose. Tis method therefore allows three-input logic function realization using single level of source-coupled pairs and ultimately resulting in signifcant reduction in minimum power supply. A total of four proposed quad-tail Hindawi Publishing Corporation VLSI Design Volume 2016, Article ID 8712768, 10 pages http://dx.doi.org/10.1155/2016/8712768