SRAM Dynamic Stability: Theory, Variability and Analysis Wei Dong Department of ECE Texas A&M University College Station, TX 77843 weidong@neo.tamu.edu Peng Li Department of ECE Texas A&M University College Station, TX 77843 pli@neo.tamu.edu Garng M. Huang Department of ECE Texas A&M University College Station, TX 77843 ghuang@neo.tamu.edu ABSTRACT Technology scaling in sub-100nm regime has significantly shrunk the SRAM stability margins in data retention, read and write operations. Conventional static noise margins (SNMs) are unable to capture nonlinear cell dynamics and become inappropriate for state-of-the-art SRAMs with shrink- ing access time and/or advanced dynamic read-write-assist circuits. Using the insights gained from rigorous nonlin- ear system theory, we define the much needed SRAM dy- namic noise margins (DNMs). The newly defined DNMs not only capture key SRAM nonlinear dynamical character- istics but also provide valuable design insights. Furthermore, we show how system theory can be exploited to develop CAD algorithms that can analyze SRAM dynamic stabil- ity characteristics three orders of magnitude faster than a brute-force approach while maintaining SPICE-level accu- racy. We also demonstrate a parametric dynamic stability analysis approach suitable for low-probability cell failures, leading to three orders of magnitude runtime speedup for yield analysis under high-sigma parameter variations. 1. INTRODUCTION Static random access memories (SRAMs) provide indis- pensable on-chip data storage and continue to dominate the silicon area in many applications. It is projected that more than 90% of silicon real estate will be occupied by SRAM in the future [1]. However, technology scaling in sub-100nm regime has significantly shrunk SRAM stability margins in data retention (standby mode), read and write [1–3]. At the same time, the susceptibility to single event upsets (SEU) induced soft errors continues to cause concerns [4]. The SRAM performance and its variability have been ex- tensively studied in the past [5–9]. In [2, 10], either simu- lation based first-order models or closed-form performance models using simple transistor models are employed to de- rive SRAM statistical performance distributions. Mixture important sampling is applied to speedup Monte-Carlo simu- lation to more efficiently capture rare failure events [11]. The same objective is approached by combining extreme value statistics theory and data filtering in [12]. Euler-Newton curve tracing is proposed to find the boundary between the success and failure regions for read access time yield analysis in [13]. A semi-analytical SRAM dynamical stability model is proposed in [14], where approximated circuit equations based on simple device models are solved in time domain. The use of piecewise linearization of circuit equations, how- ever, can lead to inaccuracy and the challenging issue of process variations is not addressed. It is important to note that stability occupies a central role in SRAM operations. While the stability in standby or hold implies proper data retention under SEUs and noise injection, stabilities in read and write correspond to non- destructive reads and successful writes, respectively. How- ever, the widely used static noise margins (SNMs) [5] cannot capture the fundamental nonlinear dynamics upon which SRAM cells operate. Although simple to obtain, SNMs as- sume the DC operation condition and are used with the assumption that timing events have infinite time duration. Due to the intrinsic complexity, dynamic noise margins are researched to a much less extent. In many ways, they may not have been defined rigorously. However, dynamic stabil- ity metrics are strongly desirable because of the following reasons. SEU and noise induced soft error analysis requires an understanding of the duration, amplitude, and charge of the injected noise and their interactions with the non- linear SRAM cell dynamics. Practically, reads and writes behave in an increasingly dynamic fashion in state-of-the- art SRAM designs with shrinking access cycle time and/or read-write-assist circuitry [3, 15]. In the latter case, well timed wordline pulses and write schemes are employed to enhance the read and write margins. Successful reads and writes depend on precise timing control where the nonlinear dynamics of SRAM cells plays a critical role. In design, bal- ance must be made between conflicting static and dynamic stability margins in hold, read and write while considering their variability. In this work, we start by developing an understanding on the basic nonlinear dynamics of SRAM cells using rigorous nonlinear system theory. In particular, we employ the no- tion of stability boundary, or separatrix [16,17], and show its central role in determining SRAM dynamic stability. Using separatrix, new dynamic noise margins (DNMs), in a way relevant to basic SRAM operations, are defined. The new DNMs not only characterize the fundamental system charac- teristics behind SRAM operations, but also provide valuable design insights by connecting dynamic stability with key de- sign parameters. Interestingly, the conventional SNMs are special cases of our more general DNMs. To embody our system concepts and DNM metrics into a practical CAD tool with SPICE-level accuracy, we show how efficient system-theoretically motivated CAD algorithms can be developed. By exploiting nonlinear system theory, a fast separatrix tracing algorithm for SRAM cells under device mismatch is developed. The entire separatrix can be ef- ficiently computed by running two special transistor-level transient simulations, achieving three orders of magnitude 978-1-4244-2820-5/08/$25.00 ©2008 IEEE 378