J Comput Electron DOI 10.1007/s10825-017-1003-x A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture Kunal Sinha 1 · Sanatan Chattopadhyay 2 · Partha Sarathi Gupta 1 · Hafizur Rahaman 1 © Springer Science+Business Media New York 2017 Abstract In this work, a germanium (Ge) fin-shaped field- effect transistor (FinFET) with silicon–germanium (SiGe) embedded source/drain architecture has been studied and the role of SiGe stressor material volume on induced channel stress has been investigated thoroughly for different stressor lengths/volumes inside the constant source/drain region. A 15-nm-long stressor from channel source/drain interface into the 50-nm-long source/drain region has been found to induce maximum compressive stress in the channel. This helps to improve the p-channel device performance and complete fill- ing of source/drain region by the same SiGe incorporate tensile channel stress which improves the n-channel device performance. The nature and amount of induced channel stress have been found to depend on the relative volume of the channel, source/drain and SiGe stressor regions. A signif- icant improvement is observed in the transconductance of the device over the drain current (g m / I d ) ratio for higher chan- nel stress, indicating better performance of amplifier using uni-axially strained channel Ge FinFET. Keywords Compressive stress · Tensile stress · FinFET · TCAD · Silicon–germanium (SiGe) 1 Introduction The performance improvement of nanoscaled field-effect transistor (FET) devices has the hindrance of power con- B Kunal Sinha kunalsinha84@yahoo.co.in 1 School of VLSI Technology, Indian Institute of Engineering Science and Technology, Shibpur, Howrah 711103, India 2 Department of Electronic Science, University of Calcutta, 92, APC Road, Kolkata 700009, India sumption, and downscaling of device dimensions led to several short channel effects (SCEs) [1, 2] and unacceptable level of leakage current [3]. To reduce the power dissipation of devices, the supply voltage scaling is used for last couple of decades [4, 5], and following the International Technology Roadmap for Semiconductors (ITRS) [6], <1 V supply volt- age is used in sub 22-nm technology node transistors now- a-days. However, the degradation of dynamic performance for supply voltage (V DD )<1 V has become very challeng- ing which reduces further when coupled with established complementary-metal–oxide–semiconductor (CMOS) tech- nology scaling [7]. To overcome these challenges, high-mobility channel material engineering [8–10], multi-gate [11] and strain engi- neering [12–14] have been attempted in recent past along with different FET structures, and the fin-shaped channel tri- gate FET (FinFET) structure, introduced by Hisamoto et al. [15], has shown the best performance with superior elec- trostatics, improved SCEs and relatively low static power dissipation. The FinFET structure has been implemented on an SOI substrate [15, 16] and bulk substrate [17] and widely investigated [15–18]. Furthermore, the use of SiGe [19], Ge [20] or III–V semiconductors [21, 22] as channel material has been studied in recent years due to the high carrier mobility in these materials, and the strain engineering for alterna- tive semiconductors represents the frontier of research for advanced optical applications [23, 24]. Germanium, a group IV material, has the advantage of direct CMOS compati- bility, and high carrier mobility enhancement makes it an excellent alternative for Si channel material. The low field electron mobility in Ge is more than double compared to Si (3900 vs. 1500 cm 2 /V-s), and the increase is fourfold for holes (1900 vs. 450 cm 2 /V-s), and thus, Ge-based FETs are very attractive for high-speed circuit applications [2]. Also, the challenges for the unstable native Ge oxide, which is criti- 123