IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 1, JANUARY 2012 157 Transactions Briefs Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops Faiz-ul-Hassan, Wim Vanderbauwhede, and Fernando Rodríguez-Salazar Abstract—In this work, we have analyzed the effects of variability, due to random dopant fluctuation (RDF), on the timing characteristics of flip-flops for the future technology generations of 25, 18, and 13 nm, based on exten- sive Monte Carlo simulations. The results show that RDF has a significant impact on all of the timing parameters and that these parameters do not follow a normal distribution; in particular, they are skewed and exhibit a large tail. Moreover, the dispersion and skewness of the timing parameters increase with technology scaling. The study of the exact shape of these dis- tributions, especially in the tail section, is of fundamental importance in the design and modeling of high-performance, reliable, and economically feasible circuits. In this paper, the distribution tails are estimated based on simulation data, with the aid of statistical nonparametric probability den- sity functions, and it has been found that timing distributions can better be represented by certain nonparametric distributions, in particular Pearson and Johnson systems. The use of these representations during the statistical static timing analysis will provide more accurate results as compared with the normal approximation of distributions and will eventually reduce the probability of yield loss. Index Terms—Device variability, flip-flops (FFs), nonparametric estima- tion, parameter fluctuations. I. INTRODUCTION Technology scaling facilitates the integration of large systems- on-chip (SoCs) with complex functionalities. In the pursuit of de- signing high-performance systems with large throughputs, the circuit speed is continuously being increased, shrinking the clock period and leaving fewer design margins. Such circuits normally incorporate deeply pipelined architectures using flip-flops (FFs), in order to meet throughput requirements. In sequential circuits, FFs are used to store the evolving system state and the speed of computation is limited by the speed at which this state can be made to change. In clock-based digital circuits, FFs are considered to be essential to meet strict timing constraints. Generally speaking, a modern digital integrated circuit without FFs is simply unthinkable. In high-performance circuits, the clock period is optimized to ob- tain the best possible performance while meeting stringent timing con- straints. The circuit performance can meet the design targets if there is a strict control over the delay of the signals arriving at the clocked el- ements (FFs). However, the signals are not completely isolated on the chip and are subjected to various sources of delay variability, such as process and environmental parameters and on-chip interconnect noise. Besides these parameters, the performance of the circuits depends on the inherent timing characteristics of the combinational logic and FFs. Manuscript received February 05, 2010; revised June 06, 2010 and September 14, 2010; accepted September 28, 2010. Date of publication November 22, 2010; date of current version December 14, 2011. F. Hassan and F. Rodríguez-Salazar are with the School of Engineering, Uni- versity of Glasgow, G12 8LT Glasgow, U.K. (e-mail: F.Hassan@elec.gla.ac.uk; F.Rodriguez@elec.gla.ac.uk). W. Vanderbauwhede is with the School of Computing Science, University of Glasgow, G12 8QQ Glasgow, U.K. (e-mail: wim@dcs.gla.ac.uk). Digital Object Identifier 10.1109/TVLSI.2010.2088409 Due to technology scaling, the performance of the circuits is becoming more sensitive to the variability in the devices so variability has be- come one of the major problems in deep-submicrometer (DSM) tech- nologies [1]–[3]. Statistical variability has become the most dominant form of variability in 45-nm technology generation [4] and is expected to further prevail in the future technology generations [5]. The design margins, which are already reduced due to the increased clock fre- quency, are greatly affected due to the variability which, in turn, limits the achievable performance and yield. In nano CMOS devices, random dopant fluctuation (RDF) is the most dominant source of statistical variability in bulk MOSFETs. The atomic-level intrinsic fluctuations in the number and location of dopant atoms in the channel region produce variations in the electrical charac- teristics of the devices (which are mainly due to difference in threshold voltage) [6]. Therefore, different transistors on the chip may exhibit large variations in the threshold voltage, resulting in delay variations of the logic gates and circuits [7]. Further, it is increasingly difficult to pre- cisely control dopant fluctuations during the manufacturing process and this problem will aggravate in DSM technologies beyond 45 nm [8]. For the timing analysis of the sequential circuits, accurate character- ization of the timing parameters of the FFs and latches is vitally impor- tant [9]. This need becomes more crucial in the design of high-speed circuits due to the strict design margins required [10]. The task be- comes more challenging when statistical device variability effects are also considered. While the maximum achievable performance and yield of a circuit depends on the magnitude of the variability in the timing pa- rameters, a better estimate of these parameters can only be made by the transient analysis of the circuits through the SPICE simulation using detailed device models. Statistical static timing analysis (SSTA) is a powerful analysis tool used in the design of digital circuits with the consideration of variability. During the SSTA of large digital circuits, the probability density function (pdf) and cumulative density function (cdf) of the timing parameters of different circuit elements are analyti- cally processed to estimate the timing characteristics of the circuit pa- rameters. The accuracy of the analysis depends on the characterization data of the individual circuit elements, accurate representation of the characterization data in the form of pdfs, and, finally, the correctness of different analytical operations used during SSTA, like min, max, or sum. In this work, we have studied the impact of statistical variations due to RDF on the timing characteristics of a standard CMOS FF. An accu- rate characterization of the timing parameters of FFs constructed with bulk MOSFETs of 25-, 18-, and 13-nm physical gate length has been performed using Monte Carlo simulations. Due to the unavailability of the characterization data from the manufacturing industry, predictive device model cards have been used. The first four moments for all of the timing parameters have been computed and can be used for estima- tion of the probability distributions. In current state-of-the-art chips, the device count has already ex- ceeded one billion, mandating the estimation of the distributions more precisely, especially in the tail regions. These distributions can then be used to estimate the probability of occurrence of specific events and, therefore, aid in the design of the system. Parametric analysis, in which a known parametric distribution (e.g., normal) is fitted on the experimental data, can be used to undertake this estimation. How- ever, the limitation of this approach is that its accuracy depends on the choice of a particular a priori density function [11]. For this reason, 1063-8210/$26.00 © 2010 IEEE