Contents lists available at ScienceDirect Solid State Electronics journal homepage: www.elsevier.com/locate/sse Temperature-dependent study of slow traps generation mechanism in HfO 2 / GeON/Ge(1 1 0) metal oxide semiconductor devices Khushabu Agrawal a,1 , Vilas Patil a,b,1 , Viral Barhate b,1 , Geonju Yoon a , Youn-Jung Lee a , Ashok Mahajan b, ⁎ ,3 , Junsin Yi a, ⁎ ,2 a College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Republic of Korea b Materials and Devices Laboratory of Nanoelectronics, Kavayitri Bahinabai Chaudhari North Maharashtra University, Jalgaon, M.S. 425001, India ARTICLEINFO Keywords: Ge MOS Atomic layer deposition HfO 2 Slow traps generation Efective oxide feld GeON passivation ABSTRACT The lower mobility for p-type Ge based is always an issue due to slow traps generation at the interface of the metal oxide semiconductor (MOS) device which designates the defects in flms generated during the deposition process. One of the efective ways to reduce this slow traps generation is to perform post deposition annealing (PDA) at a certain temperature. However, the selection of proper annealing temperature is the key to reduce defectswithoutdamagingthe flmquality.TheefectofdiferentPDAtemperaturesontheslowtrapsgeneration mechanism in the GeON passivated Ge MOS device was examined in this work. The XPS spectra show the stable formation of GeON over Ge, while HRTEM does not show any efect of PDA at the interface of GeON/Ge. The slow trap density (ΔN st )inHfO 2 /GeON/Ge interface annealed at diferent temperatures was evaluated from the hysteresis curve of C-V sweep as the function of the efective oxide feld. The lowest ΔN st (4.01 × 10 12 cm −2 ) was observed for the PDA temperature for 400 ℃. While, ΔN st increased slightly after PDA at 450 ℃. The work suggeststhatPDAatlowertemperaturesisessentialtorealizethehighqualityinterfacewithlowerinterfacetrap density, enhanced mobility and lower CET in Ge based MOS devices. Further, it also helps to reduce the slow traps generations at the interface. 1. Introduction Germanium (Ge) is being considered as an attractive channel ma- terial for the next generation complementary metal oxide semi- conductor (CMOS) devices because of its higher carrier mobility than Si. The 4 times higher hole mobility than Si makes it suitable for the p- type Ge MOS capacitors (MOSCAPs). However, the low quality inter- face formation over Ge degrades the electrical properties of the MOS device in case of direct deposition of high-k oxide on Ge [1–3]. The appropriate surface passivation is needed to achieve a high quality in- terface. The various passivation techniques have been employed by the research groups to overcome this issue. Recently, germanium oxyni- tride (GeON) has been extensively studied as it ofers the best solution to stabilize the germanium surfaces by converting native oxide into stable oxynitride [4–6]. The high quality GeON as an interfacial layer can provide the accurate passivation of the Ge substrate in terms of lower defect density and better chemical stability. Bhat et al. [7] has proposed the decoupled plasma nitridation of GeO 2 and achieved the lower defect density of (×10 11 cm −2 eV −1 ) with better thermal sta- bility.Kumaretal. [8] reportedtheformationofGe 3 N 4 asaninterfacial layer and studied the efect of post deposition annealing (PDA) en- vironment on interfacial and electrical properties of fabricated MOS devicesinwhichO 2 annealing showed better improvement in electrical properties as compared to forming gas environment. In addition to this, the HfO 2 suits well as an oxide with nitride interface gives better im- provementbecauseofitshigherkvalue(≈25)andbandgap(≈5.6eV), further, it provides the better thermal stability than the other high di- electric constant materials [9,10]. Although with this noteworthy improvement, the hole carrier mo- bilitysufersinHfO 2 basedGeMOSFETs.Ingeneral,(100)orientation https://doi.org/10.1016/j.sse.2020.107797 Received 9 October 2019; Received in revised form 20 February 2020; Accepted 4 March 2020 Abbreviations: CET, Capacitance equivalent thickness; PDA, Post deposition annealing; ΔV hys , Change in hysteresis; ΔN st , Slow traps density; E ox , Efective oxide feld; J v , Leakage current density; D it , Density of interface traps; k, Relative dielectric constant ⁎ Corresponding authors. E-mail addresses: ammahajan@nmu.ac.in (A. Mahajan), junsin@skku.edu (J. Yi). 1 Indicates equal contribution. 2 ORCID ID: 0000-0002-6196-0035. 3 ORCID ID: 0000-0003-4212-299X. Solid State Electronics 167 (2020) 107797 Available online 07 March 2020 0038-1101/ © 2020 Elsevier Ltd. All rights reserved. T