1824 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008 DC and Transient Performance of 4H-SiC Double-Implant MOSFETs Pete A. Losee, Member, IEEE, Kevin Matocha, Member, IEEE, Stephen D. Arthur, Jeffrey Nasadoski, Zachary Stum, Jerome L. Garrett, Michael Schutten, Member, IEEE, Greg Dunne, and Ljubisa Stevanovic, Member, IEEE Abstract—SiC vertical MOSFETs were fabricated and char- acterized, achieving blocking voltages around 1 kV and specific on-resistances as low as R SP,ON = 8.3 mΩ · cm 2 . DC and tran- sient characteristics are shown. Room and elevated temperature (up to 200 ◦ C) 600V/5A inductive switching performance of the SiC MOSFETs are shown with turn-on and turn-off transients of approximately 20–40 ns. Index Terms—Body diode, DMOSFET, inductive switching, SiC MOSFET. I. INTRODUCTION S ILICON carbide MOSFETs show promise for high-power- density electronic conversion. In present-day converters requiring 1000-V devices, conduction and switching losses of silicon IGBTs limit the efficiency of these converters. SiC power devices provide the opportunity for operating at both lower conduction and switching loss compared to Si IGBTs, as well as possibilities for operating at higher temperatures. Thus, operating SiC devices at higher efficiency and higher temperature enables development of high-power-density con- verters. The reliability of the SiO 2 /SiC interface at projected operating temperatures may be of concern and is currently being investigated by Matocha et al. and Singh and Hefner [1], [2]. In this paper, we report on the fabrication and charac- terization of SiC vertical MOSFETs with low on-resistance and excellent transient performance. Inductive load switch- ing is used to evaluate SiC MOSFET turn-on and turn-off performances and to characterize the devices’ internal-body- diode recovery characteristics at room- and high-temperature (200 ◦ C) operations. Manuscript received December 3, 2007; revised March 3, 2008. The review of this paper was arranged by Editor G. Pensl. P. A. Losee, K. Matocha, S. D. Arthur, J. Nasadoski, J. L Garrett, and G. Dunne are with the Semiconductor Technology Laboratory, GE Global Research, Niskayuna, NY 12309 USA (e-mail: losee@research.ge.com; matocha@research.ge.com; arthurs@research.ge.com; nasados@research. ge.com). Z. Stum is with the Micro and Nano Process Development Laboratory, GE Global Research, Niskayuna, NY 12309 USA, and also with Rensselaer Polytechnic Institute, Troy, NY 12180 USA (e-mail: Zachary.stum@research. ge.com). M. Schutten is with the Electronic Power Conversion Laboratory, GE Global Research, Niskayuna, NY 12309 USA. L. Stevanovic is with GE Global Research, Niskayuna, NY 12309 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2008.926592 Fig. 1. Gate characteristics of the 4H-SiC DMOSFET at room temperature (V DS = 0.1 V). II. DEVICE FABRICATION SiC vertical MOSFETs were fabricated on Si-face 4 ◦ off- axis 4H-SiC epilayers with a double-implanted DMOSFET process enabling submicrometer channel lengths. Two differ- ent epilayer doping concentrations were used in the experi- ment, namely, N D = 3 ×10 15 and N D = 1.4 ×10 16 cm −3 , and the thickness of the drift layer was 11 μm. A single-zone aluminum-implanted junction termination extension is used to achieve high blocking voltage. Implant activation was carried out at 1675 ◦ C. A 500-Å gate oxide was formed by thermal oxi- dation in N 2 O at 1250 ◦ C, followed by NO annealing at 1175 ◦ C for 2 h. After formation of the molybdenum gate, nickel ohmic contacts were patterned and annealed at 1050 ◦ C for 3 min in N 2 . Devices were fabricated with a total die area of 1.9 × 1.9 mm 2 and an active area of 1.96 × 10 −2 cm 2 . III. DEVICE CHARACTERIZATION A. Static Characteristics Room-temperature static characteristics of the SiC MOSFETs were measured in both packaged and wafer forms. The gate-transfer current–voltage (I –V ) characteristics of a typical device with L ch = 0.9 μm are shown in Fig. 1, exhibiting a threshold voltage of V T = 5.7 V at room temper- ature. Threshold voltages (V T )’s range from about 5.5 to 6.5 V, depending on device design, and the standard deviation across a given wafer is approximately 150 mV. Fig. 2 shows the drain I –V characteristics of a SiC MOSFET with a 0.9-μm channel length in a TO257 package. The device shown was designed with a cell pitch of 19 μm. The FET 0018-9383/$25.00 © 2008 IEEE