IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 6, DECEMBER 2004 3435 Neutron-Induced SEU in Bulk SRAMs in Terrestrial Environment: Simulations and Experiments D. Lambert, J. Baggio, Member, IEEE, V. Ferlet-Cavrois, Member, IEEE, O. Flament, Member, IEEE, F. Saigne, Member, IEEE, B. Sagnes, Member, IEEE, N. Buard, Member, IEEE, and T. Carrière, Member, IEEE Abstract—This paper investigates the sensitivity of bulk tech- nologies in the terrestrial neutron environment as a function of technology scaling. Their sensitivity is analyzed with both exper- iments and Monte Carlo simulations. The soft error rate (SER) of future technology generations is extrapolated, analyzed and dis- cussed on the basis of different parameters such as the interaction volume, the secondary ion species and the incident neutron energy ranges. Index Terms—Bulk technologies, Monte Carlo methods, neutron effects, soft error rate, single-event upset, SRAM chips. I. INTRODUCTION N EUTRON-INDUCED soft errors are now identified as a major reliability issue for complex electronic systems. At ground level, the neutrons present in the atmosphere are respon- sible of single event effects in integrated circuits [1]. The sec- ondary ions created by the interaction of neutrons with nucleus in the device are highly ionizing and can easily induce single event upsets (SEU) in static random access memories (SRAM) memories. This effect has been evidenced at avionic altitude and ground level by several studies [1], [2]. Some nuclear codes (GEANT4 [3], [4]) and some dedicated tools (BGR methods [5], SEMM [6], DASIE [7]) have been developed and used in order to predict the soft error rate (SER) and to understand the physical mech- anisms. DASIE has been developed by a CEM2-EADS collab- oration. MC-DASIE simulator, whose principles have been es- tablished by CEM2 [8], is a simulation tool based on a Monte Carlo sampling of the secondary ion to represent all cases of track location and direction and to give a statistical response of these events. The present paper discusses the trend of SER in bulk SRAMs induced by terrestrial neutrons. Some experimental data are reported in Section II. In Section III, the algorithm of the Manuscript received July 20, 2004; revised November 11, 2004. D. Lambert, J. Baggio, V. Ferlet-Cavrois and O. Flament are with the CEA/DAM-Ile de France, DCRE, 91680 Bruyères-le-Châtel, France (e-mail: damien.lambert@cea.fr; jacques.baggio@cea.fr; veronique.ferlet@cea.fr; olivier.flament@cea.fr). F. Saigne and B. Sagnes are with the Centre d’Electronique et de Micro- optoélectronique de Montpellier (CEM2), CC083, Université Montpellier II, 34095 Montpellier Cedex 05, France (e-mail: saigne@cem2.univ-montp2.fr; sagnes@cem2.univ-montp2.fr). N. Buard is with the European Aeronautic Defense and Space Company Cor- porate Research Center (EADS CCR), BP 7692152 Suresnes Cedex, France (e-mail: nadine.buard@eads.net). T. Carrière is with the European Aeronautic Defense and Space Company Space Transportation (EADS ST), 78130 Les Mureaux, France (e-mail: thierry. carriere@space.eads.net). Digital Object Identifier 10.1109/TNS.2004.839133 Fig. 1. Neutron spectrum at WNR and at ground level. MC-DASIE simulator is explained. In the fourth section, the simulation results are compared with experimental data. In the last section, we discuss on the sensitive volume obtained by simulation. Depending on the technology, we present the contribution of each type of secondary ion to the total SER and the distribution of the neutron energies which induce SEU. II. EXPERIMENTS Measurements were performed using the weapons neutron research (WNR) neutron source at Los Alamos National Lab- oratory (Beam Line 30 ). This facility provides a typical terrestrial neutron spectrum with a flux up to eight orders of magnitude higher than at ground level (Fig. 1). Three bulk SRAMs with distinct gate lengths from different manufacturers were studied: device A (500 nm), device B (250 nm) and device C (180 nm). SER testing was performed following JEDEC-JESD89 test standard for soft errors induced by neu- trons [9]. Tests were done at nominal supply voltage, which are 5 V for device A and B and 2.5 V for device C. Note that the device B and C have an internal so that the core of the device is, respectively, supplied at 1.8 V and 2.5 V. SER results are given in FIT/Mb (number of failure for a one Mb device in ). Fig. 2 shows the SER of the three SRAMs as a function of cell supply voltage considering a fluence of 14 [9]. For devices A and B, the SER is in the same order of magnitude with 866 86 and 855 116 FIT/Mb, respectively. The device C shows a much lower SER than the other parts ( 24%), at 625 65 FIT/Mb. As shown in Table I, device C uses aggressive design rules for the layout of the memory cell. Thus, the drain surface over gate length ratio is much lower for device C than for device A and B. 0018-9499/04$20.00 © 2004 IEEE