Copyright © 2012 American Scientific Publishers All rights reserved Printed in the United States of America Journal of Low Power Electronics Vol. 8, 472–484, 2012 A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation Dao-Ping Wang 1 and Wei Hwang 2 ∗ Department of Electronics Engineering and Institute of Electronics, National Chiao-Tung University, Hsinchu, 300, Taiwan (Received: 15 February 2012; Accepted: 8 June 2012) This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y -access MOS (column-direction access transistor) can improve dummy-read cells’ noise margin and isolate the pre-charge noise from bit-lines in synchronous or asynchronous clock operation. The paper also proposes a scheme of combining the row access transistor and sharing bit-line with an adjacent bit-cell. This scheme can reduce the bit-line number to half and mitigate the current consumption of the write/read buffer caused by pre- charging the bit-line to VDD. Furthermore, Y -passgate (column direction access transistor) numbers can also be reduced to half with the proposed DP 10T SRAM architecture. The result shows that write/read buffer current consumption was reduced by over 30%, compared to the conventional DP 8T structure from 1.4 V to 0.6 V VDD. Keywords: 10T, Dual-Port, SRAM, Write/Read Disturb. 1. INTRODUCTION As CMOS technology continues scaling down to deep nanometer nodes, the system-on-Chip (SOC) demands high density of embedded SRAM for high speed, low power and area improvement. In addition, it is also required more memory bandwidth. The most employed element is single-port (SP) SRAM for widely used. It con- sists of one write/read-port to activate at one time and has random access feature. However, recently demands for more memory bandwidth, the dual-port (DP) SRAM or multi-port SRAM capacity has been investigated gradu- ally, because it has parallel operation advanced feature for high speed communication and video applications which single-port SRAM does not have. The SOC chip employs dual-port or multi-port SRAM for parallel operation can improve memory bandwidth significantly. 1–5 Since SP SRAM has only 1 clock cycle to activate WL and access memory cell synchronously, the data access should execute serially. However, DP SRAM has 2 inde- pendent clock cycles which can access 2 different ports of memory cells separately and execute a parallel read or write operation. The conventional single-port and dual-port ∗ Author to whom correspondence should be addressed. Email: hwang@mail.nctu.edu.tw SRAM cell are shown in Figure 1. Though DP SRAM has such advantages of accessing cells for read and write simultaneously, it also creates some write/read disturb or conflict problems in common row access. Some techniques solve the disturb issue on synchronous DP SRAM have been reported in Refs. [6, 7]. However, in both of syn- chronous and asynchronous DP SRAM applications, the disturb issue still exist. One paper has proposed a test pro- cedure to detect the worst Vmin in asynchronous clock operation. 8 By this method, the circuit can screen the worst bit in an array which suffer write/read disturb issue. This paper proposes a method of adding Y -access MOS into the bit-cell which can solve the DP SRAM write/read disturb issue happening in common row access. The cells of the unselected column keep in a hold state by disabling Y -access MOS transistor. Therefore, the write/read-disturb phenomenon will not happen in these dummy read cells as conventional DP 8T SRAM. Furthermore, through the Y -access transistor, we also propose a scheme that con- nects adjacent cells and shares the bit-line. The bit-line number is reduced to half. Therefore the scheme can save power consumption on the bit-line when pre-charging to VDD on the dummy read cells. The rest of this paper is organized as follows. Section 2 describes the concern of the dual-port SRAM cell on 4 different operating modes to access cells within an array. 472 J. Low Power Electron. 2012, Vol. 8, No. 4 1546-1998/2012/8/472/013 doi:10.1166/jolpe.2012.1208