ORIGINAL CONTRIBUTION FPGA-Based High-Resolution DPWM Scheme Using Interleaving of Phase-Shifted Clock Pulses Kritika Bhardwaj 1 • Alok Singh 2 • Mangesh Borage 2,3 • D. S. Ajnar 1 • Sunil Tiwari 2 Received: 8 June 2018 / Accepted: 15 February 2020 Ó The Institution of Engineers (India) 2020 Abstract The digital pulse width modulation (DPWM) technique is used to generate high-frequency pulses to feed gate driver circuit of semiconductor switches in switch mode power converters. On-time of pulses can be modu- lated with the help of a digital control signal. The pro- portional change in pulse width, with the change in lowest significant bit (LSB) of control signal, gives resolution of DPWM which is generally restricted by clock frequency and number of bits used. This paper proposes a new technique to enhance the resolution of DPWM by taking the advantage of FPGA’s advanced clock management capabilities. A 13-bit DPWM scheme with 45° interleaving of phase-shifted clock pulses is implemented on a Spartan- 3AN FPGA kit using 10 MHz clock frequency to obtain the DPWM resolution of 12.5 ns, which is 8 times better than that obtained using a simple counter-based architecture. Keywords Digital pulse width modulation (DPWM)  Field programmable gate array (FPGA)  Digital clock manager (DCM)  Resolution  Linearity error  Interleaving  Counter based  Hybrid  Interleaved hybrid Introduction Electromagnets are extensively used in particle accelera- tors for bending and focusing the beam of charged parti- cles. These magnets are energized by current regulated power converters with stringent requirements on stability which ranges from few parts per million (ppm) to hundreds of ppm depending on application [1]. The stability of power converters depends on various parameters like rip- ple, regulation, time drift and temperature drift [2]. A feedback control loop is an essential part of a regulated power converter which helps in attenuating the effect of these parameters at the output. Technological advance- ments in digital hardware have made digital control tech- niques more attractive as compared to their analog counterparts because of their inherent advantages like immunity to component variations, easy implementation of sophisticated control schemes and flexibility [3]. On the contrary, digital controllers suffer from draw- backs like limited signal resolution due to finite word length of analog to digital converter (ADC), sampling time delay and occurrence of limit cycles at the output due to quantization and limited resolution of DPWM generation module [4–8]. However, these limitations can be overcome by taking due care in selection of digital hardware and adopting proper design techniques. Figure 1 shows typical block diagram of digital con- troller for a dc current regulated power converter. As shown in figure, it consists of error generation, compen- sator and DPWM generation modules, respectively, along with feedback signal conditioning and ADC circuits. The DPWM module generates gate drive pulses for semicon- ductor switches. Resolution of DPWM plays an important role in development of high-stability power converters because a & Alok Singh aloksingh@rrcat.gov.in 1 Shri Govindram Seksaria Institute of Technology and Science, Indore, India 2 Raja Ramanna Centre for Advanced Technology, Indore, India 3 Homi Bhabha National Institute, Mumbai, India 123 J. Inst. Eng. India Ser. B https://doi.org/10.1007/s40031-020-00438-9