Research Journal of Applied Sciences, Engineering and Technology 4(7): 825-832, 2012 ISSN: 2040-7467 © Maxwell Scientific Organization, 2012 Submitted: December 06, 2011 Accepted: January 10, 2012 Published: April 01, 2012 Corresponding Author: M.B.I. Reaz, Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, UKM, Bangi, Selangor, Malaysia, Tel.: +603-89216316; Fax: +603-89216146 825 Single Core Hardware Modeling of 32-bit MIPS RISC Processor with A Single Clock M.B.I. Reaz, J. Jalil and L.F. Rahman Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600, UKM, Bangi, Selangor, Malaysia Abstract: This study describes a design methodology of a single clock cycle MIPS RISC Processor using very high speed hardware description language (VHDL) to ease the description, verification, simulation and hardware realization. The RISC processor has fixed-length of 32-bit instructions based on three different format R-format, I-format and J-format, and 32-bit general-purpose registers with memory word of 32-bit. The MIPS processor is separated into five stages: instruction fetch, instruction decode, execution, data memory and write back. The control unit controls the operations performed in these stages. All the modules in the design are coded in VHDL, as it is very useful tool with its concept of concurrency to cope with the parallelism of digital hardware. The top-level module connects all the stages into a higher level. Once detecting the particular approaches for input, output, main block and different modules, the VHDL descriptions are run through a VHDL simulator, followed by the timing analysis for the validation, functionality and performance of the designated design that demonstrate the effectiveness of the design. Key words: MIPS RISC processor, register, VHDL INTRODUCTION Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can cope with designs containing hundreds of thousands of logic gates, memories, high-speed interfaces, and other high-performance components. One category of such design approaches is design methodologies based on language VHDL (Sharma et al., 2009; Mane et al., 2006). It allows designers to develop hardware systems at high level (Sulik et al., 2000). RISC or Reduced Instruction Set Computer is a design philosophy that become mainstream in the last few years, as the quest for raw speed has dominated the highly competitive computer industry. There is a desire to enhance the processor’s speed and simplify the hardware for reasons of cost. RISC design resulted in computers that execute instructions faster than other computers built of the same technology (Charles and Veljko, 1989). In a RISC machine, the instruction set is based upon a load/store approach. Only load and store instructions access memory. No arithmetic, logic or I/O instruction operates directly on memory contents. This is the key to single-cycle execution of instructions. The simplification results in an instruction decoder that is small, fast and relatively easy to design (Charles and Veljko, 1989). Due to the robust performance, simple instruction formats, breadth of products and depth of support, the MIPS RISC processor architecture becomes the market leader in high performance embedded 32-bit and 64-bit RISC processors (Sharma et al., 2009; White paper, 2011). The use of VHDL for modeling is especially appealing since it provides a formal description of the system and allows the use of specific description styles to cover the different abstraction levels (architectural, register transfer and logic level) employed in the design (Yasin et al., 2004; Reaz et al., 2007; Chen et al., 1993). In the computation of method, the problem is first divided into small pieces; each can be seen as a submodule in VHDL. Following the software verification of each submodule, the synthesis is then activated. It performs the translations of hardware description language code into an equivalent netlist of digital cells. The synthesis helps integrate the design work and provides a higher feasibility to explore a far wider range of architectural alternative (Akter et al., 2008; Reaz et al., 2003; Alvarez et al., 2011). In this study a design study of a single clock cycle MIPS RISC processor using VHDL has been presented. The goal of this work was to evaluate the feasibility of using VHDL for rapid design and prototyping of microprocessors.