0278-0070 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2018.2864238, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems SUBMITTED TO IEEE TCAD, AUGUST 2018 1 Hierarchical Verification of AMS Systems with Affine Arithmetic Decision Diagrams Carna Zivkovic (born Radojicic), Christoph Grimm, Markus Olbrich, Oliver Scharf, and Erich Barke Abstract—Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today’s analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This article shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multi-run simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phase- locked loop (PLL) of an IEEE 802.15.4 transceiver system. Index Terms—Analog Mixed-Signal Systems, Affine Arith- metic, Compositional Verification, Formal Verification. I. I NTRODUCTION Analog/Mixed-Signal (AMS) systems combine analog cir- cuits with digital hardware and software systems. A particular challenge of the analog circuit part is its sensitivity to even small variations of its parameters. Analog circuits are never absolutely accurate: Variations of parameters such as process, voltage, temperature variations, or aging, introduce deviations. Unfortunately, even small deviations can have a significant impact on the properties of a circuit or system. Therefore, verification has to show that given deviations do not cause violation of the specified properties. Additional challenges arise for AMS systems. In AMS systems, inaccuracies of analog circuits are often compensated by digital control loops, or by calibration software running on a processor. To cope with the increasing complexity and heterogeneity, AMS systems are designed and verified in a hierarchical way. At the circuit level, analog circuits are described by netlists and simulated by circuit simulators such as SPICE. Multi-run simulations (see Sec. II) determine, for given variations of parameters, an estimation of the circuit’s properties. A circuit is considered as correct if all estimated circuit properties are within the specified ranges. In a hierarchical design, the estimated properties can also be considered as a characterization of the circuit. The characterization summa- rizes the nonideal deviation from its ideal behavior. At the block diagram level, AMS systems are modeled by block diagrams and simulated by tools such as Mat- lab/Simulink or SystemC AMS. Analog blocks are described by behavioral models that implement the function, and the This work is funded within the ANCONA project (16ES021) within the program IKT 2020 by the German Ministry of Education and Research (BMBF) and by Robert Bosch AG, Intel AG, and Mentor Graphics GmbH. relevant deviations thereof. These nonideal deviations are parameters of the behavioral model. They are determined by the circuit-level verification and characterization as properties of the circuit. With the success of formal methods in the digital domain, there is a rising interest in formal verification also for AMS systems. Unfortunately, formal approaches still do not scale with their complexity and heterogeneity (see Sec. II). Even worse, it seems to be impossible to integrate formal methods into the existing ecosystem of models, languages, and tools. However, an integration with well-defined objectives might contribute to solving scalability issues by allowing a pragmatic choice between formal and simulation-based techniques. The objective and main contribution of this article is to show a way to integrate simulation-based and formal methods into a hierarchical verification flow, and to evaluate it by a challenging, industry-driven case study. Fig. ?? gives an overview of the approach. We make the following assumptions: 1) Parameters and properties of circuits and systems are real or boolean values that must be in a specified range. 2) Designers have validated behavioral models that can be considered as ‘safe abstractions’. 3) Properties of circuits describe their nonideal behavior and are parameters of the behavioral models. In order to represent properties, we use affine arithmetic decision diagrams (AADD) that we compute either by nu- merical (multi-run) simulation, or by symbolic simulation. For simplicity, we assume that there are only two levels of abstraction (circuit level, block diagram level). In Section II, we discuss previous work, and how it moti- vates the approach taken in this work. We introduce AADD in Section III. In Section IV we describe the verification flow, and how AADD are used in more detail. In Sections V, VI we describe the symbolic simulation at system- and circuit-level. In Section VII we apply the approach on a phase-locked loop (PLL) of an IEEE 802.15.4 transceiver system to demonstrate and analyze scalability, accuracy, and applicability. II. STATE OF THE ART A. Simulation-based performance verification The most common way for performance verification of AMS systems in the presence of parameter variations is a numeric simulation. A survey is given in [1]. Monte Carlo analysis computes statistical properties, in par- ticular, those of circuit properties. For Monte Carlo analysis, parameters are selected randomly in many (100s), repeated