Quality factor and frequency bandwidth of 2D self-inductors in 3D integration stacks J. Roullard a, * , S. Capraro a , E. Eid a , L. Cadix a,b , C. Bermond a , T. Lacrevaz a , A. Farcy b , B. Flechet a a Université Savoie, IMEP-LAHC – UMR CNRS 5130, 73376 Le Bourget du Lac, France b STMicroelectronics, 850 rue J. Monnet, 38926 Crolles cedex, France article info Article history: Available online 23 June 2010 Keywords: Self-inductors 3D integration Quality factor Frequency bandwidth Microwave abstract Effects due to 3D level stack on high frequency (HF) properties of 2D self-inductors integrated in the back end of line (BEOL) are investigated. Different stacking processes as Back to Face and Face to Face using a molecular SiO 2 bonding or a copper direct bonding are studied in order to determine silicon substrate stack influence on quality factor and frequency bandwidth of 2D self-inductors. Face to Face process with a molecular SiO 2 bonding allows improvements of self-inductor performances, better than Back to Face process with a molecular SiO 2 bonding and better than Face to Face process using a copper direct bonding. Ó 2010 Elsevier B.V. All rights reserved. 1. Introduction Integrated circuit (IC) technology has evolved from a transistor- centric era into a interconnect-centric era as the interconnect delay in critical paths now far exceeds the gate delay [1]. As feature sizes are further reduced to integrate more devices, the monolithic chip performance may degrade in contrast to the trend observed in semiconductor industry predicted by Moore’s law [2]. By stacking multiple devices and circuits layers, three-dimensional (3D) inte- gration enables to get a higher packing density and a lower manu- facturing cost. Chip-to-chip and intra-chip interconnection paths are reduced and 3D IC make possible the heterogeneous integra- tion using different IC technologies into the same area [3]. Never- theless the substrate stacking can increase some parasitic effects which reduce the expected benefit on global performance of 3D circuits. Major parasitic effects are the HF substrate coupling noise, additional delays on the signal propagation along interconnects be- cause the high density of via through silicon substrates (TSV) and the short proximity between silicon substrates and components can reduce quality factor of passive devices [4]. So, 3D architec- tures need to be optimized to reduce these parasitic effects and to improve HF performance of 3D circuits. The first part of this paper describes different test 3D structures stacked by Back to Face or Face to Face processes using a molecular SiO 2 bonding and stacked by a Face to Face process using a copper direct bonding. A planar self-inductors is designed in the BEOL of a 2D chip which is used as reference to quantify and to predict the previous 3D stack influence. The second part presents the extraction procedure of 2D self- inductor HF performances. This procedure can be divided in two major steps: the electromagnetic HF modelling which gives the scattering parameters S ij of the test structure and the electrical equivalent model which allows the extraction of quality factor and bandwidth frequency of the 2D self-inductor. Results about the impact of the 3D stacking on the quality factor and the frequency bandwidth of the self-inductor are given. Influ- ence of silicon thickness and silicon conductivity for the added and thinned chip and influence of thickness bonding between chips are investigated for Back to Face and Face to Face processes using a molecular SiO 2 bonding. Finally, HF quality factors of the self- inductor designed on the reference chip are compared to those ob- tained using a Face to Face stacking performed with a direct copper bonding. 2. Description of analyzed test structures The architecture of the 2D self-inductor integrated in the BEOL of the reference chip is described in Fig. 1. Upon a thick silicon sub- strate (Fig. 1a), a ground plane is patterned on the first copper layer M1 (thickness 150 nm). Next, successive silicon dioxide and copper layers (total thickness 6.8 lm) are deposited and patterned. The 2D self-inductor is integrated on the M5 and M6 metallization layers. The two turns spiral is designed with an inner area equal to 157 lm, with 3 lm spacing and 20 lm width (Fig. 1b). Many kinds of 3D integration stacking processes are actually improved, as described in [5]. Here we focus on three of them: Back 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.06.027 * Corresponding author. E-mail address: julie.roullard@univ-savoie.fr (J. Roullard). Microelectronic Engineering 88 (2011) 734–738 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee