This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications Rimesh M. Joshi, Student Member, IEEE, Arjuna Madanayake, Member, IEEE, Jithra Adikari, Member, IEEE, and Len T. Bruton, Fellow, IEEE Abstract—A broadband digital beamforming algorithm is proposed for directional filtering of temporally-broadband bandpass space-time plane-waves at radio frequencies (RFs). The enhancement of desired waves, as well as rejection of un- desired interfering plane-waves, is simulated. A systolic- and wavefront-array architecture is proposed for the real-time imple- mentation of second-order spatially-bandpass (SBP) 2-D infinite impulse response (IIR) beam filters having potential applications in broadband beamforming of temporally down-converted RF sig- nals. The higher speed of operation and potentially reduced power consumption of the asynchronous architecture of wavefront-array processors (WAPs) in comparison to the conventional synchronous hardware has emerging applications in radio-astronomy, radar, navigation, space science, cognitive radio, and wireless com- munications. Further, the bit error rate (BER) performance improvement along with the reduced computational complexity of the 2-D IIR SBP frequency-planar digital filter over digital phased array feed (PAF) beamformer is provided. A nominal BER versus signal-to-interference ratio (SIR) gain of 10–16 dB compared to case where beamforming is not applied, and a gain of 2–3 dB at approximately half the number of parallel multipliers to digital PAF, are observed. The results of application-specific integrated circuit (ASIC) synthesis of the digital filter designs are also presented. Index Terms—Array processors, bit error rate (BER), digital phased array feed (PAF), field-programmable gate array (FPGA), multidimensional digital filters, spatial modulation, systolic, wave- front, wireless. I. INTRODUCTION U LTRA-WIDEBAND (UWB) wireless communications [1]–[4], cognitive radio [5]–[8], cooperative wireless sensor networks [9], [10] require highly directional and elec- tronically steerable smart antenna arrays capable of broadband plane-wave (PW) filtering at RFs to improve the bit-error rate (BER) caused due to interference from multiple users Manuscript received May 25, 2011; revised September 05, 2011; accepted October 13, 2011. R. M. Joshi and A. Madanayake are with the Department of Electrical and Computer Engineering, University of Akron, Akron, OH 44325-3904 USA (e-mail: rmj17@uakron.edu; arjuna@uakron.edu). J. Adikari is with the Department of Electrical and Computer Engi- neering, University of Waterloo, Waterloo, ON N2L 3G1, Canada (e-mail: jithra.adikari@uwaterloo.ca). L. T. Bruton is with the Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB T2N 1N4, Canada (e-mail: bruton@ucal- gary.ca). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2011.2174167 and multipath fading. These antenna arrays typically employ beamforming using analog delay-and-sum networks, fractional delay based delay-and-sum digital networks [1], digital phased array feeds (PAFs) [11]–[13] and multi-dimensional finite-im- pule response/infinte impulse response (FIR/IIR) digital filters [5], [14]. Digital signal processing (DSP)-based broadband smart antenna arrays have potential applications in UWB wireless communications [1], [2], [15], cognitive radio [5]–[8], software-defined radio [16], microwave imaging [17], space science and radio astronomy [18]–[21], remote-sensing and navigation [22], [23]. The systolic-array and scanned-array implementation of 2-D and 3-D IIR broadband frequency-planar filters for digital beamforming have been proposed in [25]–[27]. These filters are highly suitable for high-speed filtering of broadband ST PWs based on their direction of arrivals (DOAs). For example, a 2-D IIR beam filter has recently been practically verified for balanced antipodal Viraldi antennas (BAVAs) [3], [28] using non-real time software algorithms. We propose a second-order 2-D IIR digital filter for the directional enhancement of temporally-broadband bandpass ST PWs [5], [29] (see Fig. 1). It is shown that the filter operates at an intermediate frequency (IF) leading to lower-speed VLSI circuits. We show that the proposed filters have lower computa- tional complexity compared to the conventional delay-and-sum beamformers (approximately 70% less number of multipliers for similar performance [30], [31]) and are also of lower circuit complexity compared to 2-D FIR beamformers such as fan and trapezoidal filters [29], [32]–[34]. The lower computa- tional complexity, closed-form design approach, broadband performance, electronic steerability, and availability of rapidly reconfigurable programming logic realizations make these emerging 2-D ST digital filters attractive and promising for cognitive radio applications [5]–[8]. A massively-parallel systolic-array and wavefront-array architectures are proposed for the real-time VLSI implemen- tations of the proposed digital filter. Systolic-array processors are well-known for the implementation of real-time high throughput beamforming algorithms [35]–[37]. These pro- cessors have arrays of identical processors which are highly modular, regular and highly interconnected, making them suitable for VLSI realizations for high speed, especially RF, applications [38]. This paper presents the BER performance of a second-order 2-D IIR spatially-bandpass (SBP) beam filter [39] and compares with that of a digital PAF beamformer for a 16-element uni- form linear array (ULA). The asynchronous implementations 1063-8210/$26.00 © 2011 IEEE