MAHA: A Program for Datapath Synthesis Alice C. Parker Jorge .T’ Pizarro Mitch Mlinar Department of Electrical Engineering-Systems University of Southern California Abstract MAHA is a program which implements an algorithm for register level synthesis of data paths from a data flow specification. The algorithm is based on a linear hardware assignment to critical path nodes, followed by a cost-based assignment using the concept of the freedom of a node to be scheduled. Functions with the least scheduling freedom are scheduled first. The program either minimizes cost, subject to a time constraint, or maximizes speed subject to a cost constraint. The implementation of this algorithm is presented using examples from the literature. MAHA is written in Franz LISP, and executes within minutes for problems of practical size on a VAX 11/780. 1 Introduction Register-level synthesis is composed of several tasks, in- cluding allocation of values to registers and operations to operators, scheduling when operations can or must occur, composition or construction of operators and registers from primitive components, and optimization by applica- tion of transformations and exploration of alternative designs. There are several different constraints associated with synthesis involving area, power and time minimiza- tion. For each operator, allocated area includes not only functional area, but also the associated interconnect, power and ground routing, control hardware and routing of control signals. Another important consideration in many cases is the amount of power available for the design. Finally, the overall delay allowable for completion of the operations may be highly constrained. Flexibility is important for synthesis programs to be practical. Such programs must adapt to changing con- straints as applications change, and must meet either cost or speed constraints, or sometimes both, depending on the application. Since most synthesis problems are NF’- complete, programs cannot investigate all alternatives. Thus, they must either make decisions in the ‘best* order, or must be able to backtrack or restart. Current datapath synthesis programs are experimental - they each meet some requirements, but no one existing program meets all of the above. Two related approaches which have been taken to design synthesis are EMUCS by Hitchcock [3] and an ADA to standard cell algorithm by Girczyc [I]. EMUCS is based on an algorithm by McFar- land [S] . It starts with a Value Trace representation from which tables reflecting the need to use, create, or modify a processing element in order to bind an operation to that element are created. EMUCS selects a binding which will have the smallest impact on the nodes which have not been chosen for hardware asssignment. EMUCS does not consider the critical path, and has as a single, fixed goal; the minimization of cost. The approach by Girczyc takes an ADA control/data flow graph (similar to the Value Trace) which has been functionally optimized and makes hardware assignments by adding cells composed of a register, mult.iplexer and operator. This approach does consider t.he critical path, but always attempts t.o minimize cost, subject to timing constraints. Thus, both of these approach the problem by using cost-based greedy al- gorithms. The work described in this paper is similar in intent to t,he algorithm designed by McFarland, but actually has its roots in a control synthesis algorithm developed by Nagle 171. Nagle’s notion of freedoms (attraction weights) has been directly applied to this research. In order for a program to meet the requirements on flexibility, a program has to make decisions in some order such that earlier decisions do not overly constrain later decisions. It must also have some method for computing the effect of a single design decision on the overall cost and speed of the resulting hardware. Thus, the synthesis problem we describe is as follows: The program must input a data flow description of the hardware behavior, and must output a datapath structure, consisting of registers, operators, and required interconnec- tions, along with a time schedule giving the ordering of operations. The program must make the most constrained decisions first, so that the ordering of decisions does not greatly affect the optimality of the resulting design. The program should adjust either to cost or speed constraints, and it should be able to measure the impact of each design decision, to avoid large amounts of searching of the design space. Finally, the program should be able to restart or 23rd Design Automation Conference 0738-100X/88/0000/0481$01.00 01988 IEEE Paper 27.2 461