A New NMOS Four-Quadrant Analog Multiplier Boonchai Boonchu Mahanakorn University of Technology, 51 Cheum-Sampan Road, Nong-chock District, Bangkok, Thailand, 10530 Email: boonchai@mut.ac.th Wanlop Surakampontorn Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Ladkrabang, Bangkok 10520, Thailand. Email: kswanlop@kmitl.ac.th Abstract—In this paper, an all NMOS voltage-mode four- quadrant analog multiplier based on a basic NMOS differential amplifier that can produce the output signal in voltage form without using resistors is presented. The proposed circuit has been simulated with SPICE and achieved -3dB bandwidth of 120MHz. The power consumption is about 3.6mW from a ±2.5V power supply voltage, and the total harmonic distortion is 0.85% with a 1V input signal. 1. INTRODUCTION An analog multiplier is an importance basic building block for the design of analog nonlinear function circuits. It is found application in, for examples, automatic gain control, frequency translation, waveform generation, linear modulation, neural networks, and other signal processing circuits. Usually, the variable transconductance technique which operates on Gilbert’s translinear circuit is widely used for the design of multiplier circuits in Bipolar and CMOS technologies [1], [2], [3]. The other approaches in CMOS technology are that based on square-law characteristics of MOS transistor which are biased in saturation region [4], [5], [6], and that based on the current- voltage characteristics of MOS transistor in the non- saturation region [7]. Unfortunately, all the mention techniques require resistors to obtain the output signal in voltage form. The use of resistors may require external resistors, or occupy large chip area to implement in IC form and also cause of the multiplier frequency degradation. Only few types of the multipliers that can produce the output voltage without the use of resistors [8], [9]. The multiplier proposed in this paper uses the non-linear characteristic of the NMOS differential amplifier based upon the quarter- square algebraic identity. But, however, the proposed circuit also does not require resistors to obtain the output signal in voltage form. 2. CIRCUIT DESCRIPTIONS The basic principle of the proposed multiplier is based on the quarter-square algebraic identity, (V 1 +V 2 ) 2 -(V 1 -V 2 ) 2 = 4V 1 V 2 . For this operation, the multiplier needs the summing and squarer circuits. The multiplier is achieved in three steps. First, the sum and difference of the two input voltages are formed. Then, these summing and differencing results are squared. Finally, the multiplication is obtained by subtracting the square of the difference from the square of the sum of the two inputs. 2.1 Summing Circuit Fig. 1 shows the fully differential summing circuit that based on basic MOS differential pairs M 1 -M 4 and the active loads M 5 -M 6 . Assuming that transistors M 1 -M 4 are matched with transconductance parameter K 1 and transistors M 5 -M 6 are matched with K 5 . If all devices operate in saturation region, applying the differential input voltages V 1 and V 2 , the loop equations of the gate-to-source voltages of the two differential amplifiers M 1 -M 2 and M 3 -M 4 can be written as 2 1 2 1 2 2 gs gs V V V V − = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + (1) 4 3 2 1 2 2 gs gs V V V V − = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + − (2) where V gs1 to V gs4 are the gate-to-source voltage of the transistors M 1 -M 4 . By replacing TH d gs V K I V + = into above equations, we can write 1 2 1 1 2 1 2 2 K I K I V V d d − = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + (3) 1 4 1 3 2 1 2 2 K I K I V V d d − = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + − (4) Subtracting (3) by (4), the result can be expressed as ( ) ( ) ( ) ( ) { } 3 2 4 1 1 2 1 1 d d d d I I I I K V V + − + = + (5) Considering from the two differential amplifiers M 1 -M 2 and M 3 -M 4 in Fig. 1, we can see that I d1 =I d4 and I d2 =I d3 . Then, (5) can be rearranged and rewritten in the form of 1004 0-7803-8834-8/05/$20.00 ©2005 IEEE.